Control Circuits; Control Circuit Operation Overview - Epson DFX-8500 Service Manual

2.3 CONTROL CIRCUITS

Figure 2-15 shows a block diagram of the control circuits, with the C204 main board at the center.

CONTROL CIRCUIT OPERATION OVERVIEW

The core of the control circuit is the TMP95C061AF CPU (IC2). This CPU is driven using a 24.57 MHz
external clock (CRU1). The CPU executes programs stored in the PROM (IC5). The CPU starts executing a
program upon receiving the reset signal from an external device via the gate array E05B36 (IC1). The CPU
accesses the internal and external RAM (IC14). The CPU also controls the EEPROM (IC11), used to store
parameters, such as the tear-off position, while the printer is turned off.
The CPU controls all printer operations via the peripheral IC E05B36 (IC1). The main functions of the
E05B36 (IC1) are:


/CS (Chip Select) signal creation


Address decoding and latching


Clock pulse creation


Printhead driver control


Carriage driver control


Encoder pulse circuit control


Platen gap and HF phase signal creation


Interface control


Monitoring of the carriage and paper feed motor drivers for abnormal current.


Reset signal creation


PSB/PSE board control


LED control


Reading the DIP switch settings on the C204 SUB board
Signals such as DRERR (driver error) and PD (power down), are sent to the C204 PSB/PSE board to
provide back-up control of the EEPROM (when the printer is turned off) and control of the power supply
voltage. When the CPU receives a POFF or CL signal, the CPU turns off the power supply voltage of the
C204 PSB/PSE board by outputting a /PD signal.
The reset circuit outputs the reset signal when the printer is turned on or off, the voltage level drops, or a
reset signal is input from an external device. It resets the control circuit for a certain period, directly or via
the gate array (E05B36).
OPERATING PRINCIPLES
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