Control Circuits; Control Circuit Operation Overview - Epson DFX-5000+ Service Manual

Control Circuit
Figure 2-18 shows a block diagram of the control circuit with the C117 MAIN
board assembly at the center.

Control Circuit Operation Overview

The core of the control circuit is the TMP96C14 CPU (ICl). This CPU is driven
using a 14.74 MHz external clock (CRU 1). The CPU executes programs stored in
the internal mask ROM and 1M external PROM (IC4). The CPU starts executing
a program upon receiving the reset signal from an external device (ICS, IC9). The
CPU accesses the internal RAM and external PS-RAM (256K) memories. The
CPU also controls the non-volatile memory (IC2) used to store the parameters,
such as the tear offposition, while the printer is turned off. The CPU controls all
the printer operations via the peripheral ICs and controls the printer mechanism
and interfaces by writing directly to the ports. The CPU controls the E05A87 gate
array (IC7) via the address bus (MMIO: Memory Mapped Input/Output).
The main functions of the E05A87 gate array are: CS (Chip Select) signal
creation, address decoding, printhead driver control, carriage driver control,
encoder pulse circuit control, PG and fan motor phase signal creation, interface
control, CR and PF motor driver abnormal sensor circuit control, reset signal
creation, control signal creation for the power supply board, control of the LEDs
on the Cl 17 PNL board assembly, and reading the DIP switch settings.
Signals, such as DRERR, VPC, and CLIMIT (power down), are connected to the
Cl 17 power supply board assembly to provide back-up control ofthe non-volatile
memory (when the printer is turned off) and control ofthe power supply voltage.
When the CLIMIT signal informs the CPU that the power has been turned off (or
that the power supply voltage has dropped), the CPU turns offthe power supply
voltage from the Cl 17 power supply board assembly by outputting the CLIMIT
signal.
EPSON DFX-5000+ Service Manual
Operating Principles
2-21