Nmi Mask Register; Pic - Toshiba T2200SX User Manual

The RAM parity check is not used in this system. Therefore, when the I/O port '061' bit-7 is read,
this bit is always '0'.
The cause and control ports of the NMI are shown in Table 2-2.
RAM Parity Error
I/O Channel Error

2.4.1 NMI Mask Register

An NMI is generated by an I/O channel error. An I/O channel error may occur in the expansion port
or when a microprocessor of the intelligent power supply generates the error. System software can
disable the NMI using the NMI mask register. This register is assigned to I/O port address '070.'
The bit assignment of this register is as follows:
7
MASK
Bit 7: Mask: A "0" enables the register to generate the NMI signal which is then sent to the
Bits 6 - 0:

2.4.2 PIC

There are two 82C59A equivalent Programmable Interrupt Controllers (PICs) contained in the SI
T9901 to handle 15 levels of maskable interrupts. Programming these devices can mask each
interrupt level on and off. STI and CLI instructions enable and disable all maskable interrupts.
2-14
Table 2-2 NMI
NMI Mask *control
P - '61' bit-2
(1 = Disable)
P - '61' bit-3
(1 = Disable)
6 5
--- --- ---
Central Processor, while "1" disables the NMI signal. This bit will be set to
"1" at system power on.
Reserved
Check status
P - '61' bit-7
(1 = Enable)
P - '61' bit-6
(1 = Enable)
Bit
4 3 2
--- ---
1 0
--- ---