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SNUESIGBEE3
Parallel/Serial
(8-bit
Shift'
Output
(S/L)
15v1smn
On
H
Load
Vcc
715
I3
I4
I6
srwv
14
Q..
Load
Senal
Input
a
c
A
4
3
2
,
5¢f1a1
a
c
A
Input
(son
CK
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Clear
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A
3
1
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1
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ax
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V
»
0
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o
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cts
U,
Q
_
1
z
1
2D
ID
Cm:
IQ
ZCR)
Serial
Input
Register)
(Cm
E
Cleo?
F
G
9
ll
IO
12
F
E
G
Cho#
Clock
gp(
u
Innubil
,
7
a
5
s
Clock
ow
0
Clock
(CK)
Inhibit
lg"
5"4I
1
3
1
Q
I'
§
|»
1
5
2
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VAT'
5
5
F1
Se'a1
Sh'f|
f
1
Loiilnmw
Time
Chart
(SNHLSISSP)
5-42
Triagered
9'
Clear)
with
wx)
40
ann
40
50
15
9
IO
H
'
ctn
Q,
cn
'
'
'
11
§
fj
7
5
5
4
GND
30
30
20
Synchronized
5-41
select
2
states.
can
shift
from
Serial
Shift
the
data
(A-H).
input
parrallel
(SI),
when
QH
output
possible.
becomes
clock
pulse.
when
shift/load
is
(A-H)
input
first
loaded
with
with
parrallel
clock
A-H
to
QH
inhibit
clock
shift
level,
can
valid
when
CRFH
| ' * " ] Q
f f
Q
:
'|
E
1'
'
!
L
1
1
1|
1
5
1
1
O
5
i
i
1
i
f
i
2
J
1
F f ' 1 l ¥ 3
; - L i I ~ 1 L 1 » L _ _ r ~ 1 _
ri
]
I
Senal
:g
{<
=
;
p
5-43
consists
relation
the
shows
Table
except
is
the
same
"/
Du
load
parallel
(SI)
serial
input
in
order
from
H
to
QH
two
inputs
Having
input
output
one
(S/L)=H,
shift
load
is
This
input
(A-H)
Parallel
input
this
(S/L)=L.
In
with
first
loaded
clock.
This
clock
Then,
input
inputs.
in
(during
order
will
clock
(CI)=I-I,
done.
be
Clear
shift
is
done
at
'
"
'
Sum
_--
_
.
of
6
piece
is
table
shown
at
of
HD74LS74AP
same
one
(PS).
preset
HD74LS74AP
as
bit
shift
8
register
output
QH.
to
in
parrallel
serial
(A-H)
and
of
serial
belongs
to
serial
input
(SI)
by
shifted
to
QH
possible
becomes
Parrallel
case,
This
clock
clock.
is
synchronizing
is
shifted
by
when
load,
period,
if
and
shift,
not
is
independently
(CR)
clock.
of
rising
edge
.
Flop.I/O
D
Flip
This
table
5-14.
Relation
I/O
Timechart
The
I/O
is
1
L
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