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REQUl@f
Inverter
Trigger
4
3
2
4
o
-r---
oas
u
L5
(HD74LS|4P)
5-2|
Input
HDZ4ES3d§
I
NAND
Positive
(8-input
0
NC
pq
NC
I
D
I
ll
'il
K
(SV)
VCC
4B
4A
4Y
38
Il
IO
un
as
nz
f ' i D 1 |
i D 1
'TH V415 | "f\
V!7\ Hn Hnnfr'
za
aa
IA
ua
nv
'
s-23
E-lDT4|i$I4AE§
Edge-Triggered
(Dual
D-Type
(SV)
IZCR)
ZCLR
20
2c><
vee
ni
M'
|;
.;
E
cx 'f
*.;.' ' . ; f ' . ; i L ; . V
. ;
li!
'.;J
C33§T8E1%§:
Inverter
Inverter
Regular
Trigger
Schmitt
Inverter
Gate)
V
NC
ll
I
GND
3A
3Y
9
B
av
cnc
Flop)
Flip
26
20
zvn
|o
9
|
I
cuvu
$3527
EYSEEM
circuit
diagram,
MB689O
In
shown
opposite.
5-22
8
input
In
figure
Ouput
Input
goes
L.
CUf"SiS'CS
Figure
5-23
gates.
CDl'1Si5t5
Figure
5-24
IC's.
The
is
the
Data
input
of
(CK)
clock
pulse
(§
is
becomes
H
L)
Q
(5
and
becomes
L
L
Q
is
L.
The
diagram
opposite
in
table
5-3
and
the
shown
in
Figure
5-25.
inverters
two
IC.
NAND
gate
when
all
the
L
goes
(A-G)
H.
Output
are
the
when
of
input
H
one
of
of
4pcs
2
input
of
2
D
Flip
Flop
pcs
is
read
rising
(D)
at
then
transferred
be
when
(PR)input
pre-set
is
H)
when
clear
(CLR)
is
condition
described
a
of
edge
trigger
state
are
is
or
edge
to
output;
goes
input
is
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