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simple
a
higher
the
*HALT
A
Low
the
end
without
ing
the
processor
*HALT
A
Low
end
of
loss
of
the
buses
the
processor
'k
\
Available,
Bus
The
BA
makes
the
that
imply
Low,
an
The
BS
state(valid
interrup
vector
ing
of
indication
device.
by
Acknowledge
Sync
synchronization
Halt/Bus
condition.
R/C
network
may
threshold
voltage
before
reset
state
level
this
input
on
instruction
of
the
present
When
loss
of
data.
buses
high
impedance.
are
is
in
the
Halt
level
this
input
on
the
instruction
present
When
data.
halted,
high
impedance.
are
is
in
the
Bus
Status(BA,BS)
is
indication
output
an
buses
the
MOS
of
will
the
bus
be
additional
dead
cycle
signal,
when
output
with
leading
|
as
BA
0
0
1
0
0
1
1
1
is
Acknowledge
fetch(RES,NMI,FIRQ,IRQ,SWI,SWI2,SWI3).
the
lower
four
address
of
which
interru
is
indicated
interrupt
on
an
is
Grant
when
true
be
used
to
reset
that
all
ensures
the
Processor.
the
pin
will
cause
remainhelted
and
the
halted,
BA
output
is
also
BS
Bus
Grant
state.
or
will
the
MPU
cause
and
remain
halted
the
is
BA
output
is
also
BS
High
Halt
Grant
State,
or
Bus
internal
of
an
high
impedance.
MPU
available
for
more
will
before
elapse
decoded
with
BA,
of
edge
Q).
State
MPU
Definition
stare
MPU
Normal
(Running)
RESET
Acknowledge
Interrupt
or
SYNC
Acknowledge
HALT
Bus Grant
or
th§_indicated
during
lines,can
provide
'
level
b
eing
t
is
p
whi
le
the
MPU
line.
the
HD6809
is
in
11
entire
the
system.This
peripherals
out
are
running
MPU
to
stop
indefinitely
is
driven
High
which
indicates
High
running
to
stop
indefinitelywithout
driven
High
indicating
which
indicates
control
signal
which
This
does
signal
than
cycle.
when
one
the
MPU
acquires
representing
the
MPU
both
cycle
of
hardware
a
This
signal,
plus
the
with
user
an
served
and
allow
vectoring
is
waiting
for
external
Halt
Bus
Grant
a
or
of
at
indicat-
the
the
at
not
BA
goes
the
bus.
decod-
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