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Table
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BM
I
Mode
K B N M 1 P r ? h ' b i
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0
en
1
pro
3.
C-REG-SEL
in
table
shown
As
(IC64-IC68).
Decoder
6-3-2
Address
Decoder
circuit
Address
decoder
which
is
area
Decoder-
ROM
Address
(1)
Allocated
address
Address
ROM
ROM,
20
pin
(Chip
decoder
the
In
bit
3
AB15,
AB14,
Output
YO-Y3
$2,000
address
is
level,
H
dsssds
in
Table
6-5
expansion
from
system
number
20
of
of
I/Q
Sygtem
I/0
address
(2)
System
I/O
register
is
shown
circuit
shown
As
dsssdsr
13
bit
addregg
$8
putted
as
a
Further,
this
in
ICII
and
each
pond
to
s-3
c-neo-sen.
Register
GC.
Mode
g Characteq
0
s'
1
Graphic
function
&4
Register
H
i
|
55
Mode
I
i
0
KBIRQProhi
Mode
g
Op
U
e
2)
it
1
Read/Write
6-3.
Circuit
divided
is
to
follows:
as
IC2-ICS
is
of
Decoder
circuit
Pin).
Fig
6-3
Select
circuit
shown
at
of
the
address
AB13
level
of
L
signal
ICII,
from
address
$8,000.
outputted
signals
are
20
pin
(below),
to
connector
d e C O d e r
address
IC5,
($ppQQ~$FFEF)
addregg
circuit.
dgggdgr,
which
(SFFOO-SFFEF)
Figure
6-4.
at
in
circuit
Figure
A315-A33
bus
gf
address
block
from
signal
is
decoded.
generatesthe
ICl3,
I/O
address.
system
4 5
function
ic
RV
Meds
t Uanormali
O
1
Q
everse
0
0
1 i0
1
0
1
1
1
1
1
r
n
Sl.
HR
KN
|
YSHIFTIA
o
o
o
|
I
0
0
1
h 9 7 J 7 ' L M O d e - L E D
information
registers
circuits
depending
3
table
6-5.
shown
at
level
signal
L
supply
main
describes
the
6-3,
figure
Input
connected.
bus
are
is
outputted
When
mask
ROM
the
as
per
These
of
IC2-ICQ.
and
expansion
RAM
signal
is
outputted
internal
from
This
circuit
is
internal
register
input
of
6-4,
Level
connected,
L
are
the
address
SFFCO,
bit
address
by
lower
3
address
signal
dccodØ
QØigiki?-Y
B
R
0
0
Black
Blue
0
1
I
0
Red
1
1
Magenta
0
Green
1
Cyan
0
Yellow
White
1
Function
Mode
ON
'LED
ou
to
RAM
address
on
each
When
address
each
ROM
to
circuit.
has
of
ICII
upper
the
At
the
block
of
as
signal
ROMKIL
allocated
address
ROM IL
signals
comes
At
pin
connector.
after
getting
register
by
IC33
dsssdsrthe
system
Main
address.
ICl2
has
upper
is
signal
out-
6-6).
(Table
of
AB2-ABO
which
corres-
ri
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