The Phase Sensitive Detectors - Stanford Research Systems SR865 Operation Manual

Chapter 2
The input to the Y PSD is a third sine wave, computed by the SR865, shifted by 90° from
the second sine wave. This waveform is sin(ω
The phase shifts (θ
0.000001°. Neither waveform is actually output in analog form since the phase sensitive
detectors are actually digital multipliers inside the SR865.
Phase Jitter
When an external reference is used, the phase-locked loop contributes a little phase jitter.
The internal oscillator is supposed to be locked with zero phase shift relative to the
external reference. Phase jitter means that the average phase shift is zero but the
instantaneous phase shift has a few microdegrees or millidegrees of noise. This shows up
at the output as noise in phase or quadrature measurements.
Phase noise can also cause noise to appear at the X and Y outputs. This is because a
reference oscillator with a lot of phase noise is the same as a reference whose frequency
spectrum is spread out. That is, the reference is not a single frequency, but a distribution
of frequencies about the true reference frequency. These spurious frequencies are
attenuated quite a bit but can still cause problems. The spurious reference frequencies
result in signals close to the reference being detected. Noise at nearby frequencies now
appears near dc and affects the lock-in output.
Phase noise in the SR865 is very low and generally causes no problems. In applications
requiring no phase jitter, the internal reference mode should be used. Since there is no
PLL, the internal oscillator and the reference sine waves are directly linked and there is
no jitter in the measured phase. (Actually, the phase jitter is the phase noise of a crystal
oscillator and is very, very small).
Harmonic Detection
It is possible to compute the two PSD reference sine waves at a multiple of the internal
oscillator frequency. In this case, the lock-in detects signals at N× f
synchronous with the reference. The SINE OUT frequency is not affected. The SR865
can detect at any harmonic up to N=99 as long as N × f

The Phase Sensitive Detectors

The amplified input signal is converted to digital form using A/D converter sampling at
10 MHz. The SR865 then multiplies the signal with the reference sine wave digitally.
The dynamic reserve is limited by the quality of the A/D conversion. Once the input
signal is digitized, no further errors are introduced. Certainly the accuracy of the
multiplication does not depend on the size of the numbers. The A/D converter used in the
SR865 is extremely linear, meaning that the presence of large noise signals does not
impair its ability to correctly digitize a small signal. In fact, the dynamic reserve of the
SR865 can exceed 120 dB without any problems. We'll talk more about dynamic reserve
a little later.
We've discussed how the digital signal processor in the SR865 computes the internal
oscillator and two reference sine waves and handles both phase sensitive detectors. In the
and the 90° shift) are exact numbers and accurate to better than
ref
t + θ
+ 90°).
r ref
ref
does not exceed 2.5 MHz.
ref
SR865 DSP Lock-in Amplifier
Basics 43
which are