Module Identiþcation; Timing Performance; Local Bus To Dram Cycle Times - Motorola MVME177 Installation And Use Manual

Functional Description
Local Bus Time-out
4
Module Identification

Timing Performance

Local Bus to DRAM Cycle Times

4-18
The MVME177 provides a time-out function for the local bus. When
the timer is enabled and a local bus access times out, a Transfer
Error Acknowledge (TEA) signal is sent to the local bus master. The
time-out value is selectable by software for:
8 µsec
64 µsec
256 µsec
Infinite
The local bus timer does not operate during VMEbus bound cycles.
VMEbus bound cycles are timed by the VMEbus access timer and
the VMEbus global timer. Refer to the VMEchip2 in the Single Board
Computers Programmer's Reference Guide for detailed programming
information.
Software distinguishes between an MVME177 module and an
MVME176 module by use of the I/O control register (GPI) bit 3. On
an MVME177, the I/O control register (GPI) bit 3 is out (open) for a
ÒhighÓ (one). On an MVME176, the I/O control register (GPI) bit 3
is hardwired in (shorted) for a ÒlowÓ (zero).
This section provides the performance information for the
MVME177. Various MVME177s are designed to operate at 50 MHz
or 60 MHz (when supported by 060).
The PCCchip2 and VMEchip2 have the same local bus interface
timing as the MC68060, therefore the following cycle times also
apply to the PCCchip2 and the VMEchip2. Read accesses to