Table of Contents
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hardware interrupts
software-programmable 4-17
hardware preparation 2-4
headers 2-10
hexadecimal character 1-12
host port B-34
host system B-35
I
I/O interfaces 4-11
IACK (interrupt acknowledge) 2-13
installation instructions 2-10
Intel 82596 LAN Coprocessor Ethernet
driver B-20
interrupt acknowledge (IACK) 2-13
Interrupt Stack Pointer (ISP) B-11
interrupts 4-17
introduction 1-1, 2-1, 3-1, 4-1, A-1
IOC (I/O Control) B-17
IOI (Input/Output Inquiry) B-16
IOP (Physical I/O to Disk) B-16
IOT (I/O Teach) B-17
IOT command parameters C-5
IOT command parameters for supported
floppy types C-5
ISP (Interrupt Stack Pointer) B-11
italic strings B-28
J
J1 2-6
J10 2-8
J2 2-6
J3 4-20
J6 2-7, 2-10
J7 2-7, 2-10
I
J8 2-7, 2-10
J9 2-8
N
jumpers 2-4, 2-10
D
E
L
X
LAN (see 82596CA and Ethernet) 4-15
LAN Coprocessor Ethernet Driver B-20
IN-8
LAN DMA transfers 4-20
LAN FIFO buffer 4-19
LAN transceiver 2-16
LEDs 3-3
levels of implementation A-3
LFM (linear feet per minute) 1-3
linear feet per minute (LFM) 1-3
Local Area Network (see LAN) 4-15
local bus 4-18
local bus access 4-18
local bus memory map 3-4, 3-5
local bus time-out 4-18
local bus to DRAM cycle times 4-18
local I/O devices memory map 3-6
local reset (LRST) 3-2, 3-8
local reset operation 3-8
local resources 4-16
location monitors 2-16
logical unit number (LUN) (see CLUN or
DLUN)
longword 1-12
lowercase command entry B-26
LRST (local reset) 3-2, 3-8
LUN (logical unit number) (see CLUN or
DLUN)
M
mantissa field B-45
manual terminology 1-12
MC68040 TRAP instructions B-36
MC68060 MPU 4-4
MCECC 1-7
memory maps
local bus 3-4
local I/O devices 3-6
memory requirements B-11
metasymbols B-28
middle-of-the-road EIA-232-D configu-
ration A-5
minimum EIA-232-D connection A-6
MK48T08 (see Battery Backed Up RAM,
BBRAM, and NVRAM) 4-10
Index
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