Motorola MVME177 Installation And Use Manual page 48

Operating Instructions
3
Address Range
$FFF00000 - $FFF3FFFF
$FFF40000 - $FFF400FF
$FFF40100 - $FFF401FF
$FFF40200 - $FFF40FFF
$FFF41000 - $FFF41FFF
$FFF42000 - $FFF42FFF
$FFF43000 - $FFF430FF
$FFF43100 - $FFF431FF
$FFF43200 - $FFF43FFF
$FFF44000 - $FFF44FFF
$FFF45000 - $FFF451FF
$FFF45200 - $FFF45DFF Reserved
$FFF45E00 - $FFF45FFF Reserved
$FFF46000 - $FFF46FFF
$FFF47000 - $FFF47FFF
$FFF48000 - $FFF4FFFF
$FFF50000 - $FFF6FFFF
$FFF70000 - $FFF76FFF
3-6
2. This area is user-programmable. The suggested use is shown in
the table. The DRAM decoder is programmed in the MCECC chip,
and the local-to-VMEbus decoders are programmed in the
VMEchip2.
3. Size is approximate.
4. Cache inhibit depends on devices in area mapped.
5. This area is not decoded. If these locations are accessed and the
local bus timer is enabled, the cycle times out and is terminated by
a TEA signal.
6. The SRAM has optional battery backup on the MVME177.
The following table focuses on the Local I/O Devices portion of the
local bus Main Memory Map.
Table 3-2. Local I/O Devices Memory Map
Devices Accessed
Reserved
VMEchip2 (LCSR)
VMEchip2 (GCSR)
Reserved
Reserved
PCCchip2
MCECC #1
MCECC #2
MCECCs (repeated)
Reserved
CD2401 (Serial Comm. Cont.) D16-D8
82596CA (LAN)
53C710 (SCSI)
Reserved
Reserved
Reserved
Port Size Size
-- 256KB
D32 256B
D32-D8 256B
-- 3.5KB
-- 4KB
D32-D8 4KB
D8 256B
D8 256B
-- 3.5KB
-- 4KB
512B
-- 3KB
-- 512B
D32 4KB
D32/D8 4KB
-- 32KB
-- 128KB
-- 28KB
Notes
5
1,4
1,4
5,7
5
1
1
1
1,7
5
1,9
7,9
1,9
1,8
1
5
5
6