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ES3880FL (IC101) : MPEG decoder
1. Terminal layout
80 ~ 51
1 ~ 30
3. Pin function
Pin No.
Symbol
I/O
1
VDD
-
3.3V power supply
2
RAS#
O
Row address strobe
3
DWE#
O
DRAM write enable
4~12
DA0~8
O
DRAM multiplexed row and column address bus
13~28
DBUS0~15
I/O
DRAM data bus
29
RESET#
I
System reset
30
VSS
-
Ground
31
VDD
-
3.3V power supply
32~39
YUV0~7
O
YUV[7:0] 8-bit video data bus
40
VSYNC
I/O
Vertical sync
41
HSYNC
I/O
Horizontal sync
42
CPUCLK
I
RISC and system clock input. CPUCLK is used
only if SEL_PLL[1:0] = 00 to bypass PLL.
43
PCLK2X
I/O
Doubled 54MHz pixel clock
44
PCLK
I/O
27MHz pixel clock
45~49
AUX0~4
I/O
Auxiliary control pins 4:0
AUX0 and AUX1 are open collectors.
50
VSS
-
Ground
51
VDD
-
3.3V power supply
52
AUX6
I/O
Auxiliary control pins 6
53
AUX5
I/O
Auxiliary control pins 5
54
AUX7
I/O
Auxiliary control pins 7
55~62
LD0~7
I/O
RISC interface data bus
63
LWR#
O
RISC interface write enable
64
LOE#
O
RISC interface output enable
65
LCS3#
O
RISC interface chip select
66
LCS1#
O
RISC interface chip select
67
LCS0#
O
RISC interface chip select
68~79
LA0~11
O
RISC interface address bus
80
VSS
-
Ground
81
VPP
-
5.0V power supply
2. Block diagram
Processor
Interface
LA[17:0]
LD[7:0]
LCS3#, LCS#[1:0]
LWR#
RISC
LOE#
Processor
ACLK
ATCLK
Serial
AIN
Audio
Serial Audio
AOUT
Interface
ARFS
Interface
ATFS
ARCLK
SEL_PLL[1:0]
TDM
TDM
TDMCLK
Interface
Interface
TDMDR
TDMFS
Function
Pin No.
82~87
88
89
90
91
92
93
94
95
96
97
98
99
100
DRAM Interface
Huffman
Decoder
2Kx32 ROM
512x32 SRAM
MPEG
Processor
64x32 ROM
32x32 SRAM
Video Output
Registers
On Screen
Display
DRAM DMA
Controller
Symbol
I/O
LA12~17
O
RISC interface address bus
ACLK
I/O
Master clock for external audio DAC
AOUT
O
Audio interface serial data output when
selected.
SEL_PLL0
I
System and DSCK output clock
frequency selection at reset time. The
matrix below lists the available clock
frequencies and their respective PLL
bit settings.
SEL_PLL1
SEL_PLL0
0
0
0
1
1
0
1
1
ATCLK
I/O
Audio transmit bit clock
ATFS
O
Audio transmit frame sync
SEL_PLL1
I
Refer to the description and matrix for
SEL_PLL0 pin 89.
DA9
O
DRAM multiplexed row and column
address line 9
DOE#
O
DRAM output enable
AIN
I
Audio serial data input
I
Audio receive bit clock
ARCLK
ARFS
I
Audio receive frame sync
TDMCLK
I
TDM serial clock
TDMDR
I
TDM serial data receive
TDMFS
I
TDM frame sync
CAS#
O
DRAM column address strobe
VSS
-
Ground
MX-G950V/MX-G880V
MX-G850V/MX-G750V
RAS#
DA[9:0]
DBUS[15:0]
DRAM
DOE#
DWE#
CAS#
AUX
AUX[7:0]
YUV[7:0]
PCLK2X
Screen
PCLK
Display
VSYNC
HSYNC
CPUCLK
Misc.
RESET#
Function
DCLK
Bypass PLL (input mode)
54MHz (output mode)Default
67.5MHz (output mode)
81.0MHz (output mode)
1-43
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