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238
A
B: P
B
PPENDIX
ATH
UILDER
Setting up a Virtual
Circuit
Early and Partial Packet
Discard
T1/E1 UNI with IMA
Interface
S330/S310 M
A
ODULE AND
PPLICATION
To configure a circuit in the PathBuilder S330/S310, you must set up a virtual
circuit between any two ports through the CTX. See "Configuring Virtual Circuits"
in Chapter 4, for details about setting up virtual circuits.
VPI and VCI Ranges
As explained earlier in this chapter, address translation is performed in the CTX.
For VP connections, the full 8 bits of the VPI is looked up, so up to 256 VP
connections are supported per port. For VC connections, only two LSB VPI bits and
8 LSB VCI bits are considered. So, for VC connections, VPs 0 through 3 and VCs 1
through 255 are the only ones supported.
Early packet discard (EPD) and partial packet discard (PPD) functions are provided
on the CTX for every connection. EPD and PPD are enabled per VC for those VCs
carrying AAL5 traffic.
For EPD, every output queue contains two thresholds that you can set: congestion
ON and congestion OFF. You set these thresholds by percentage. See "Setting
Congestion Thresholds" in Chapter 4, for details about setting congestion
thresholds. Partial packet discard works when the queue is actually full and a cell is
dropped for a particular connection. When this happens, the rest of the cells for
that connection are discarded until the end of packet is reached.
The four T1/E1 UNI with IMA interfaces allow you to connect legacy, voice, video,
and data traffic to your branch offices, using either single T1s/E1s or nxT1/nxE1
IMA bundles. The IMA bundles connect up to four lines from a single office site
(eight lines if you have installed the optional four-port IMA expansion module).
The PathBuilder S310 switch has only a single T1/E1 interface.
On the T1/E1 receive side, the data flow is as follows:
A line interface unit recovers the digital data and performs the T1/E1 framing
on it with DSX and CSU capability. The integral CSU eliminates the need for an
external CSU.
The data flows through a framer to get the ATM cells.
The output of the framer interfaces to the IMA circuitry that stores the data
into memory and synchronizes the cells back. All four T1s/E1s go into the IMA
buffers where they can be treated as one group or as four separate groups
(four individual T1s/E1s).
After the cells are synchronized, the IMA circuitry tags them with a group
number and passes them to the CTX. At the CTX interface, the cells will look
like they are coming from different groups.
On the T1/E1 transmit side, the data flow is as follows:
Cells received from the CTX toward the T1/E1 groups are stored in the
corresponding buffers, as described under "CTX Output Queues and Memory
Partition" earlier in this chapter. Group 1 consists of 4 buffers; the other three
groups have two buffers each.
The cells are picked up from the queues in order of priority, under the shaper
control, and delivered to the IMA logic.
O
VERVIEW
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