Icom ID-RP2 Service Manual page 65

The oscillated signal at the 1st VCO is buffer amplified at
Q473 and then passed through the bandpass filter (L474–
L477, C488–C497).
The filtered signal is applied to the buffer amplifier (Q710)
and then applied to the T/R switch (D710, D711).
The receive 1st LO signal from the T/R switch (D711) is ap-
plied to the 1st mixer circuit (IC71).
The transmit signal from the T/R switch (D710) is applied to
the 1st mixer circuit (IC960).
4-3-3 2ND PLL CIRCUIT (MAIN-D UNIT)
The 2nd PLL circuit oscillates the 2nd LO frequency, and
the signal is applied to the 2nd mixer circuit and quadrature
modulator.
The signal oscillated at the 2nd VCO circuit (Q631, D630) is
amplifi ed at the buffer amplifi ers (Q632, Q633), then applied
to the PLL IC (IC550, pin 19). The applied signal is divided
at the prescaler and programmable counter section by the
N-data ratio from the CPU (LOGIC-D unit; IC50). The divided
signal is detected on phase at the phase detector using the
reference frequency (X400: 15.3 MHz) and output from pin
13 (IC550). The detected signal is passed through the loop
fi lter (R555–R557, C564, C567) and then applied to the 2nd
VCO circuit via the mode switch (IC551, pins 1, 7).
The oscillated signal at the 2nd VCO is amplifi ed at the buf-
fer amplifiers (Q632 Q771), and is then applied to the T/R
switch (D770, D771).
The receive 2nd LO signal from the T/R switch (D771) is ap-
plied to the 2nd mixer circuit (Q131).
The transmit signal from the T/R switch (D770) is applied to
the quadrature modulator (IC890).
• PLL CIRCUIT
IC551
Mode
switch
Loop
filter
Loop
filter
Q400
Buffer
Q632
2nd VCO
Buffer
Q631, D630
IC550
LPF
PLL IC
1st VCO
Buffer
Q473
Q471, Q472,
D471
IC400
LPF
PLL IC
15.3 MHz
4-4 POWER SUPPLY CIRCUITS
4-4-1 LOGIC-D UNIT VOLTAGE LINE
Line
Common 5 V controlled by the +5 V regula-
tor circuit (IC500, Q500, Q501) using the
5V "PWRS" signal from the CPU (IC50, pin
101). The output voltage is applied to the
baseband filters (IC300–302), etc.
Common 3.3 V converted from the 5V line
by the 3.3V regulator circuit (IC502). The output
3.3V
voltage is applied to the FPGA IC (IC200) and
buffer amplifier (IC901), etc.
Common 3.3 V converted from the 5V line
by the 3.3V regulator circuit (IC504). The output
3.3V
voltage is applied to the CPU (IC50) and A/D
converter (IC55), etc.
Q771
to quadrature modulator (Tx)
Buffer
D770
Buffer
to 2nd mixer circuit (Rx)
Q633
D771
2ND PLL CIRCUIT
1ST PLL CIRCUIT
Q710
to 1st mixer circuit (Tx)
Buffer
D710
Buffer
Q474
D711
X400
D - 4 - 4
Description
to 1st mixer circuit (Rx)