Icom ID-RP2 Service Manual page 10

SECTION 3
3-1 RECEIVED DATA PROCESS
3-1-1 DURING ASSIST REPEATER OPERATION
(MAIN UNIT)
The demodulated data signal from the connected ASSIST
repeater (ID-RP2L) is applied to [ASSIST-1 A/B] (J13) or
[ASSIST-2 A/B] (J12) connector. The demodulated data sig-
nal is applied to the LVDS receivers (IC25, IC26) and con-
verted to the I/O signal and then applied to the ASSIST I/F
FPGA IC (IC19).
The ASSIST I/F FPGA IC (IC19) converts the applied I/O
signal format to the ATM-SAR interface signal format.
The converted ATM-SAR interface signal is applied to the
ATM-SAR controller (IC16) and converts the data format
into the PCI bus line data format.
The converted data signal is applied to the PCI/DMA FPGA
IC (IC15).
3-1-2 DURING LOCAL REPEATER OPERATION
(MAIN UNIT)
The demodulated data signal from the connected LOCAL
repeater (ID-RP2D or ID-RP2V) is applied to [LOCAL RPT-
CONT I/O] connector (J10). The applied signal is amplified
at the buffer amplifiers (IC17, IC20, IC21, IC23) and then
applied to the LOCAL RPT I/F FPGA IC (IC24).
The LOCAL RPT I/F FPGA (IC24) detects header frame
synchronization and then converts the format into the serial
data signal.
The converted serial data signal is applied to the PCI/DMA
FPGA IC (IC15).
• REPEATER CONTROL CIRCUIT
ID-RP2C
CPU
IC5
SRAM
IC2, IC3,
IC6, IC7
Ethernet
Gateway
controller
Server
IC8
etc.
10BASE-T
CIRCUIT DESCRIPTION
PCI/DMA
FPGA
LOCAL BUS
IC15
PCI BUS
3-1-3 DURING CONNECTED SERVER OPERATION
(MAIN UNIT)
The data signal from the connected server is applied to the
[10BASE-T] connector (J1) and then applied to the Ethernet
controller (IC8). The Ethernet controller (IC8) converts the
data format into the PCI bus line data format.
The converted signal is applied to the PCI/DMA FPGA IC
(IC15).
3-1-4 SRAM CIRCUIT (MAIN UNIT)
The PCI/DMA FPGA IC bridges the data signal from the
ATM-SAR controller (IC16), LOCAL RPT I/F FPGA (IC24)
or Ethernet controller (IC8) to the SRAM circuit.
The bridged data signal from the PCI/DMA FPGA IC (IC15)
is applied to the SRAM circuit (IC2, IC3, IC6, IC7) and then
memorized for transmission.
The bridged data signal from the PCI/DMA FPGA IC (IC15)
is also applied to the CPU (IC5) and the CPU analyzes
the call sign settings. The CPU (IC5) selects the desired
repeater or connected server for transmission according to
the analyzed call sign settings.
3-2 TRANSMIT DATA PROCESS
3-2-1 SRAM CIRCUIT (MAIN UNIT)
The memorized data from the SRAM circuit is transferred to
the desired repeaters or connected server at the PCI/DMA
FPGA IC according to the analyzed call sign settings at the
CPU.
The data signal from the SRAM circuit (IC2, IC3, IC6, IC7)
is applied to the PCI/DMA FPGA IC (IC15) and the PCI/
DMA FPGA IC (IC15) selects one of the ATM-SAR control-
ler (IC16), LOCAL RPT I/F FPGA (IC24) or Ethernet con-
troller (IC8) by the CPU (IC5).
LOCAL
RPT I/F
amplifier
FPGA
IC17, IC20,
IC24 IC21, IC23
ATM-SAR ASSIST
controller I/F
FPGA
IC16
IC19
B - 3 - 1
LOCAL REPEATER
Buffer
ID-RP2D/
ID-RP2V
ASSIST REPEATER
LVDS
driver
ID-RP2L
IC22
LVDS
receiver
IC25, IC26