Icom ID-RP2 Service Manual page 64

4-2-4 1ST MIXER CIRCUITS (MAIN-D UNIT)
The 1st mixer circuits convert to the RF signal with the 1st
LO signal.
The fi ltered signal from the low-pass fi lter (L892, L893, C904
–C908) is applied to the 1st mixer circuit (IC960, pins 1, 6).
The applied signal is mixed with the 1st LO signal coming
from the 1st VCO circuit (Q471, Q472, D471) via the buffer
amplifiers (Q473, Q710) to convert into the RF signal. The
RF signal from the 1st mixer circuit (IC960, pin 6) is passed
through the bandpass fi lter (FI961) and then amplifi ed at the
RF amplifi er (IC1021).
The amplified signal is passed through the bandpass filter
(FI1020) to suppress spurious components and then applied
to the drive/power amplifi er circuits.
4-2-5 DRIVE/POWER AMPLIFIER CIRCUITS
(MAIN-D UNIT)
The drive/power amplifi er circuits amplify the RF signal to the
output level.
The filtered RF signal from the bandpass filter (FI1020) is
amplifi ed at the pre-drive (Q1080), drive (Q1081) and power
(IC1160) amplifi ers to obtain a stable 10 W of output power.
The power amplifi ed signal from the power amplifi er (IC1160,
pin 4) is passed through the antenna switch (D1160), SWR
detector circuit (D1166, D1167), low-pass filter which con-
tains strip-line and C1198, and then applied to the antenna
connector (CASE; W4) via J1 (CHASSIS-D).
4-2-6 APC CIRCUIT (MAIN-D UNIT)
The APC circuit protects the driver and power amplifi ers from
a mismatched output load and stabilizes the output power.
The SWR detector circuit (D1166, D1167) detects the for-
ward signals and refl ection signals, and converts it into DC
voltage. The output voltage is at a minimum level when the
antenna impedance is matched with 50 Ω and is increased
when it is mismatched.
• APC CIRCUIT
HV
T+9
RF signal
from 1st mixer
circuit
PCON
Q1250
Q1082
PRE
DRIVE
IC1251
IC1250
+
APC
APC
AMP.
AMP.
–
APC circuit
The detected voltage is applied to the APC amplifier
(IC1250, pins 3, 4) and is compared with the reference volt-
age which is supplied from the CPU (LOGIC-D unit: IC50,
pin 85) as "PCON" signal.
When antenna impedance is mismatched, the detected volt-
age exceeds the power setting voltage. The output voltage of
the APC amplifi ers (IC1250, IC1251) controls the bias volt-
age of the drive amplifiers (Q1080, Q1081) and to reduce
the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUITS (MAIN-D UNIT)
The PLL circuit provides stable oscillation of the 1st LO fre-
quencies and 2nd LO frequency. The PLL output compares
the phase of the divided VCO frequency to the reference
frequency. The PLL output frequency is controlled by the di-
vided ratio (N-data) of a programmable divider.
4-3-2 1ST PLL CIRCUIT (MAIN-D UNIT)
The 1st PLL circuit oscillates the 1st LO frequencies, and
signals are applied to the 1st mixer circuits. The oscillated
signals from the 1st VCO circuit (Q471, Q472, D471) are
applied to the buffer amplifi ers (Q473, Q474) and are then
applied to the PLL IC (IC400, pin 6).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc.
The applied signal is divided at the prescaler and program-
mable counter section by the N-data ratio from the CPU
(LOGIC-D unit; IC50). The divided signal is detected on
phase at the phase detector using the reference frequency
(X400: 15.3 MHz) and output from pin 4 (IC400). The output
signal is passed through the loop fi lter and is then applied to
the 1st VCO circuit.
Q1081
Q1080
DRIVE
AMP.
D - 4 - 3
IC1160
FOR
POWER
AMP.
REV
D1167
D1166
to antenna
connector