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Principles of Operation
The third 1/0 port (read-only) may be interrogated
by other Multibus masters to determine the processor
status (see paragraph 3-23). In addition, three jumper
selectable inputs are user configurable and may be
read by any Multibus master, including the GDP.
These inputs may be used to specify user-dependent
configuration options (such as CRT model selection).
The fourth 110 port (read-only) supplies the GDP
with a unique processor ID. This processor ID is used
by the GDP during initialization to determine pro-
cessor dependent parameters.
4.11 CIRCUIT ANALYSIS
The schematic diagram for the iSBC 432/100 board
is given in figure 5-2. The schematic diagram consists
of 7 sheets, each of which includes grid coordinates.
Signals that traverse from one sheet to another are
assigned grid coordinates at both the signal source
and the signal destination. For example, the grid
coordinates 2Bl locate a signal source (or signal
destination) on sheet 2 in zone Bl.
Both active-high and acitve-low signals are used. A
signal mnemonic that ends with a virgule (e.g.,
DA T7 /) denotes that the signal is active-low
(~
0.4V). Conversely, a signal mnemonic without a
virgule (e.g., BYTOP) denotes that the signal is
active-high(~
2.0V).
4.12 INITIALIZATION
When the Multibus INIT I signal is activated, the
iSBC 432/100 Processor Board is forced into the
following state:
1. The GDP is initialized and held in the initialized
state by pulling the PIN IT I signal low (through
flip-flops A22 and A24 at 4D6 and 4D4).
2. The data transfer state machine is initialized to
state zero (by the PINIT I input to latch A25 at
4C4).
3. The bus interrupt flip-flop, A22 (4D6), is
cleared.
4.
The external "stop" command flip-flop, A26
(4C6), is cleared.
5. The bus arbiter is reset (outputs are 3-stated).
6.
The serial 1/0 port is set to the "idle" mode.
4.13 CLOCKGENERATION
The CPU clock is generated by two flip-flops (in Al
at 5C6) from a master oscillator (Al2 at 5D7). The
resulting overlapped CPU clock phases (CLKA and
CLKB) are driven through a resistive termination by
50-ohm line drivers (A2 at 5C5). In addition, CLKA/
is driven to v,arious positions on the board by a
4-8
iSBC 432/100
separate 50-ohm line driver (A3 at 5C5). CLKA/
controls the timing of the address counters, the
transfer counter, and the data transfer state machine.
The 110 clock is developed by an 8284 clock
generator (A41 at 3D6) and crystal Yl (14.7456
MHz). This frequency is internally divided by six
within the 8284 to provide a 2.4576 MHz master
clock to the 8251A USART (A21 at 3C4). This clock
is also divided by two by flip-flop A23 (3D4) to
supply a 1.2288 MHz clock to the 8253 PIT (A36
at 3B4).
4.14 iAPX432GENERAL
DAT A PROCESSOR
As discussed previously, the GDP outputs the
address and operation code on the ACD bus in two
double-byte cycles (paragraph 4-1). During a write
cycle, the write data immediately follows these two
double-byte addressing specification cycles. The tim-
ing of a typical processor write cycle is illustrated in
figure 4-6 while the timing of a typical read cycle is
illustrated in figure 4-7. The information contained
within the 8-bit operation code is shown in figure 4-8.
4.1 S ADDRESS GENERATION
At the start of a data tr an sf er operation, the comple-
ment of the transfer length is latched into the transfer
up-counter (A57 at 7C3). The access type, operation
type, and least-significant address bit (odd/even flag)
are clocked into latch A38 (7C3). Discrete logic gates
(A58 and Al4 at 7B2) generate the CNTl signal
(from the output of the transfer counter) that is used
by the data transfer state machine to determine when
the last data byte is transferred. At the same time, the
least significant address byte (output by the processor
on
ACDO-ACD7)
is
latched
into
two
4-bit
up-counters, A33 and A34 (6B4).
The second double-byte issued by the procesor
(upper 16 address bits) is divided into three portions.
The upper four bits are discarded. The lower four
bits are routed directly to a 4-bit up-counter, Al 7
(6B4). The remaining eight bits are routed to two
4-bit adders (AlS and Al6 at 6C6) where they are
combined with the address offset from Al8 (4A6).
The resulting address is
latch~d
into two 4-bit
up-counters (A3 l and A32 at 6C4) to complete the
generation of a 20-bit Multibus address.
4.16 DATATRANSFERSTATE
MACHINE
The heart of the data transfer state machine. is an
82Sl00 PLA (A28 at 4C3). The eight output signals
of the PLA are divided into three segments: a 4-bit
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