Figure 19-15 Horizontal Sync Pulse Timing In Tft Mode; Figure 19-16 Vertical Sync Pulse Timing Tft Mode - Motorola DragonBall MC9328MX1 Reference Manual

H_WIDTH
LSCLK
HSYNC
OE
DATA
VSYNC
Figure 19-15. Horizontal Sync Pulse Timing in TFT Mode
Figure 19-16 shows the vertical timing (timing of one frame). The delay from the end of one frame until
the beginning of the next is programmable. The memory timing signal parameters are:
• V_WAIT_1 is a delay measured in lines. For V_WAIT_1= 1 there is a delay of one HSYNC
(time = one line period) before VSYNC. The HSYNC pulse is output during the V_WAIT_1 delay.
• For V_WIDTH (vertical sync pulse width) = 0, VSYNC encloses one HSYNC pulse.
For V_WIDTH = 2, VSYNC encloses two HSYNC pulses.
• V_WAIT_2 is a delay measured in lines. For V_WAIT_2 = 1, there is a delay of one HSYNC
(time = one line period) after VSYNC. The HSYNC pulse is output during the V_WAIT_2 delay.
End of frame
VSYNC
HSYNC
OE
V_WAIT_1
MOTOROLA
H_WAIT_2
V_WIDTH
(lines)
Figure 19-16. Vertical Sync Pulse Timing TFT Mode
LCD Controller
LCDC Operation
XMAX H_WAIT_1
Beginning of frame
YMAX
V_WAIT_2
19-17