Interrupt Enable Register Low; Table 10-9 Interrupt Enable Register Low Description - Motorola DragonBall MC9328MX1 Reference Manual

10.4.5.2 Interrupt Enable Register Low

INTENABLEL
BIT 31 30 29
TYPE rw rw rw
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Table 10-9. Interrupt Enable Register Low Description
Name
INTENABLE Interrupt Enable—Enables/Disables the individual bit interrupt sources
Bits 31–0 to request a normal interrupt or a fast interrupt. When INTENABLE is
set and the corresponding interrupt source is asserted, the interrupt
controller asserts a normal or a fast interrupt request depending on the
associated INTTYPEH and INTTYPEL setting.
MOTOROLA
Interrupt Enable Register Low
28 27 26 25
INTENABLE [31:16]
rw rw rw rw
0 0 0 0
12 11 10 9
INTENABLE [15:0]
rw rw rw rw
0 0 0 0
Description
Interrupt Controller (AITC)
24 23 22 21 20
rw rw rw rw rw
0 0 0 0 0
0x0000
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0x0000
Programming Model
Addr
0x00223014
19 18 17 16
rw rw rw rw
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
Settings
0 = Interrupt disabled
1 = Interrupt enabled
and generates a
normal or fast
interrupt upon
assertion
10-13