Chipset - SOYO SY-K7V DRAGON Plus User Manual

Motherboard Description SY-K7V DRAGON Plus!

1-9 CHIPSET

VIA Apollo KT266A
The KT266A and VT8233CE chipset is a high performance, cost-effective
and energy efficient system controller for the implementation of AGP / PCI
desktop personal computer systems based on 64-bit Socket-A (AMD Athlon)
processors.
The chip set consists of the KT266A system controller (552 pin BGA) and
the VT8233CE V-Link south bridge (376 pin BGA). The KT266A Host
system controller provides superior performance between the CPU, DRAM,
AGP bus, and V-Link bus with pipelined, burst, and concurrent operation.
The VT8233CE V-Link Client controller is a highly integrated PCI / LPC
controller.
Its internal bus structure is based on 33 MHz PCI bus that provides 2x
bandwidth compare to previous generation PCI / ISA bridge chips. The
VT8233CE also provides a 266MB/sec bandwidth Host/Client V-Link
interface with V-Link-PCI and V-Link-LPC controllers. It supports five PCI
slots of arbitration and decoding for all integrated functions and LPC bus.
The KT266A supports eight banks of DDR SDRAM up to 4 GB. The
DRAM controller supports standard Synchronous DRAM (SDRAM), and
Virtual Channel SDRAM (VC SDRAM) SDRAM in a flexible mix / match
manner, or it can be configured to support Double-Data-Rated (DDR)
SDRAM mode. The DDR DRAM interface allows zero wait state bursting
between the DRAM and the data buffers at 66 / 100 / 133 MHz. The eight
banks of DRAM can be composed of an arbitrary
mixture of 1M / 2M / 4M / 8M / 16M / 32M / 64M xN DRAMs. The
DRAM controller also supports optional ECC (single-bit error correction
and multi-bit detection) or EC (error checking) capability separately
selectable on a bank-by-bank basis. The DRAM controller can run either
synchronous or pseudo-synchronous mode with the host CPU bus frequency
(100 / 133 MHz).
The KT266A Host system controller also supports full AGP v2.0 capability
for maximum bus utilization including 2x and 4x mode transfers, SBA
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