Intel BX80605I5760 Specification page 9

Errata (Sheet 1 of 5)
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B-1
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Specification Update
Status
No Fix The Processor May Report a #TS Instead of a #GP Fault
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
No Fix Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to Memory-Ordering Violations
Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher
No Fix
Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
No Fix MOV To/From Debug Registers Causes Debug Exception
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to
No Fix
Partial Memory Update
No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
IRET under Certain Conditions May Cause an Unexpected Alignment Check
No Fix
Exception
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be
No Fix
Preempted
General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit
No Fix
Violation above 4-G Limit
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs
No Fix
in 64-bit Mode
No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
Corruption of CS Segment Register During RSM While Transitioning From Real
No Fix
Mode to Protected Mode
Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy
No Fix
Counter may be Incorrect
No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed
No Fix Delivery Status of the LINT0 Register of the Local Vector Table May be Lost
No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not
No Fix
Provide Correct Exception Error Code
Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is
No Fix
Set on a #GP Instruction
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/
No Fix POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point
Exception
No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1
The Memory Controller tTHROT_OPREF Timings May be Violated During Self
No Fix
Refresh Entry
No Fix Processor May Over Count Correctable Cache MESI State Errors
ERRATA
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