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AAN46.
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also
Result in a System Hang
Problem:
Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a
system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in
another machine check bank (IA32_MCi_STATUS).
Implication:
Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang
and an Internal Timer Error to be logged.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN47.
IA32_PERF_GLOBAL_CTRL MSR May be Incorrectly Initialized
Problem:
The IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [34:32] may be incorrectly set to 7H
after reset; the correct value should be 0H.
Implication:
The IA32_PERF_GLOBAL_CTRL MSR bits [34:32] may be incorrect after reset
(EN_FIXED_CTR{0, 1, 2} may be enabled).
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN48.
Performance Monitor Interrupts Generated From Uncore Fixed
Counters (394H) May be Ignored
Problem:
Performance monitor interrupts (PMI's) from Uncore fixed counters are ignored when
Uncore general performance monitor counters 3B0H-3BFH are not programmed.
Implication:
This erratum blocks a usage model in which each of the cores can sample its own
performance monitor events synchronously based on single interrupt from the Uncore.
Workaround:
Program any one of the Uncore general performance monitor counters with a valid
performance monitor event and enable the event by setting the local enable bit in the
corresponding performance monitor event select MSR. For the usage model where no
counting is desired, program that Uncore general performance counter's global enable
bit to be zero.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN49.
Performance Monitor Counter INST_RETIRED.STORES May Count
Higher than Expected
Problem:
Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used to track
retired instructions which contain a store operation. Due to this erratum, the processor
may also count other types of instructions including WRMSR and MFENCE.
Implication:
Performance Monitoring counter INST_RETIRED.STORES may report counts higher than
expected.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
31
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