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AAN124.
DTS Temperature Data May Be Incorrect On a Return From the
Package C6 Low Power State.
Problem:
The DTS (Digital Thermal Sensor) temperature value may be incorrect for a small
period (less than 2ms) after a return from the package C6 low power state.
Implication:
The DTS temperature data (including temperatures read by Platform Environment
Control Interface) may be reported lower than the actual temperature. Fan speed
control or other system functions which are reliant on correct DTS temperature data
may behave unpredictably.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN125.
Unexpected DMI and PCIe Link Retraining and Correctable Errors
Reported
Problem:
When the processor exits the package C6 power state, the PCIe and DMI ports may
enter a state where they will NAK all packets for a short time. If this condition persists
long enough so that the same packet is NAKed four times, the link will retrain and a
correctable error may be signaled by the PCIe end point. Overall performance of the
link is not impacted.
Implication:
Due to this erratum, unexpected link retraining and correctable errors may be reported.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN126.
QPI Lane May Be Dropped During Full Frequency Deskew Phase of
Training
Problem:
A random QPI Lane may be dropped during the lane deskew phase while the QPI Bus is
training at full frequency.
Implication:
When there are multiple resets after the QPI Bus has reached full speed operation there
is a small chance that a lane could be dropped during the deskew phase of training. In
the case of a lane being dropped this will be detected and a retry will be done until the
link is established and the lane is re-trained.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN127.
PerfMon Overflow Status Can Not be Cleared After Certain Conditions
Have Occurred
Problem:
Under very specific timing conditions, if software tries to disable a PerfMon counter
through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter event-
select (e.g. MSR 0x186) and the counter reached its overflow state very close to that
time, then due to this erratum the overflow status indication in MSR
IA32_PERF_GLOBAL_STAT (0x38E) may be left set with no way for software to clear it.
Implication:
Due to this erratum, software may be unable to clear the PerfMon counter overflow
status indication.
Workaround:
Software may avoid this erratum by clearing the PerfMon counter value prior to
disabling it and then clearing the overflow status indication bit.
Status:
For the steppings affected, see the Summary Tables of Changes.
52
Specification Update
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