Intel BX80605I5760 Specification page 12

Errata (Sheet 4 of 5)
Steppings
Number
B-1
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12
Status
VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET NMI
No Fix
Blocking
Intel® VT-d Receiving Two Identical Interrupt Requests May Corrupt Attributes of
No Fix Remapped Interrupt or Hang a Subsequent Interrupt-Remap-Cache Invalidation
Command
No Fix S1 Entry May Cause Cores to Exit C3 or C6 C-State
Multiple Performance Monitor Interrupts are Possible on Overflow of
No Fix
IA32_FIXED_CTR2
No Fix LBRs May Not be Initialized During Power-On Reset of the Processor
Unexpected Interrupts May Occur on C6 Exit If Using APIC Timer to Generate
No Fix
Interrupts
LBR, BTM or BTS Records May have Incorrect Branch From Information After an
No Fix
EIST Transition, T-states, C1E, or Adaptive Thermal Throttling
No Fix PECI GetTemp() Reads May Return Invalid Temperature Data in Package C6 State
PECI PCIConfigRd() Followed by a GetTemp() May Cause System Hang in
No Fix
Package C6 State
PECI Mailbox Commands During Package C6 Idle State Transitions May Result in
No Fix
Unpredictable Processor Behavior
No Fix VMX-Preemption Timer Does Not Count Down at the Rate Specified
Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter
No Fix
0
No Fix SVID and SID of Devices 8 and 16 only implement bits [7:0]
No Fix No_Soft_Reset Bit in the PMCSR Does Not Operate as Expected
No Fix VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct Operand Size
PCIConfigRd() and PCIConfigWr() PECI Commands May Silently Fail During
No Fix
Package C6 Exit Events
Performance Monitoring Events STORE_BLOCKS.NOT_STA and
No Fix
STORE_BLOCKS.STA May Not Count Events Correctly
No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
No Fix
Transitions
INVLPG Following INVEPT or INVVPID May Fail to Flush All Translations for a
No Fix
Large Page
No Fix The PECI Bus May be Tri-stated After System Reset
No Fix LER MSRs May Be Unreliable
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB
No Fix
Error
No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints
No Fix An Exit From the Core C6-state May Result in the Dropping of an Interrupt
No Fix PCIe Extended Capability Structures May be Incorrect
No Fix PMIs During Core C6 Transitions May Cause the System to Hang
No Fix IA32_MC8_CTL2 MSR is Not Cleared on Processor Warm Reset
ERRATA
Specification Update