Table of Contents
Advertisement
AAN26.
Processor May Over Count Correctable Cache MESI State Errors
Problem:
Under a specific set of conditions, correctable Level 2 cache hierarchy MESI state errors
may be counted more than once per occurrence of a correctable error.
Implication:
Correctable Level 2 cache hierarchy MESI state errors may be reported in the
MCi_STATUS register at a rate higher than their actual occurrence.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN27.
Synchronous Reset of IA32_APERF/IA32_MPERF Counters on
Overflow Does Not Work
Problem:
When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its
maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously
reset to 0x0 on the next clock. This synchronous reset does not work. Instead, both
MSRs increment and overflow independently.
Implication:
Software can not rely on synchronous reset of the IA32_APERF/IA32_MPERF registers.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN28.
Disabling Thermal Monitor While Processor is Hot, Then Re-enabling,
May Result in Stuck Core Operating Ratio
Problem:
If a processor is at its TCC (Thermal Control Circuit) activation temperature and then
Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a
subsequent re-enable of Thermal Monitor will result in an artificial ceiling on the
maximum core P-state. The ceiling is based on the core frequency at the time of
Thermal Monitor disable. This condition will only correct itself once the processor
reaches its TCC activation temperature again.
Implication:
Since Intel requires that Thermal Monitor be enabled in order to be operating within
specification, this erratum should never be seen during normal operation.
Workaround:
Software should not disable Thermal Monitor during processor operation.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN29.
PECI Does Not Support PCI Configuration Reads/Writes to Misaligned
Addresses
Problem:
The PECI (Platform Environment Control Interface) specification allows for partial reads
from or writes to misaligned addresses within the PCI configuration space. However,
the PECI client does not properly interpret addresses that are Dword (4 byte)
misaligned and may read or write incorrect data.
Implication:
Due to this erratum, writes to or reads from Dword misaligned addresses could result in
unintended side effects and unpredictable behavior.
Workaround:
PECI host controllers may issue byte, word and Dword reads and writes as long as they
are aligned to Dword addresses.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
25
Hide quick links:
Advertisement
Table of Contents
