Table of Contents
Advertisement
AAN77.
VM Exits Due to "NMI-Window Exiting" May Be Delayed by One
Instruction
Problem:
If VM entry is executed with the "NMI-window exiting" VM-execution control set to 1, a
VM exit with exit reason "NMI window" should occur before execution of any instruction
if there is no virtual-NMI blocking, no blocking of events by MOV SS, and no blocking of
events by STI. If VM entry is made with no virtual-NMI blocking but with blocking of
events by either MOV SS or STI, such a VM exit should occur after execution of one
instruction in VMX non-root operation. Due to this erratum, the VM exit may be delayed
by one additional instruction.
Implication:
VMM software using "NMI-window exiting" for NMI virtualization should generally be
unaffected, as the erratum causes at most a one-instruction delay in the injection of a
virtual NMI, which is virtually asynchronous. The erratum may affect VMMs relying on
deterministic delivery of the affected VM exits.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN78.
Malformed PCIe Packet Generated Under Heavy Outbound Load
Problem:
When running the PCIe ports in a 2x8 configuration at 5.0GT/S speed with heavy
outbound write traffic, malformed packets could be generated. The length in the header
field will not match the actual payload size.
Implication:
Due to this erratum, malformed PCIe packets could be transmitted.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN79.
PCIe Operation in x16 Mode With Inbound Posted Writes May be
Unreliable
Problem:
Under a complex set of conditions, it is possible that with PCIe configured for x16
operation inbound writes may store incorrect data.
Implication:
PCIe operation with inbound writes in x16 mode may be unreliable.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN80.
Unpredictable PCI Behavior Accessing Non-existent Memory Space
Problem:
Locked instructions whose memory reference is split across cache line boundaries and
are aborted on PCI behind Intel® 5 Series Chipset and Intel® 3400 Series Chipset may
cause subsequent PCI writes to be unpredictable.
Implication:
Aborted split lock accesses to non existent PCI memory space behind Intel 5 Series
Chipset and Intel 3400 Series Chipset may cause PCI devices to subsequently become
inoperable until a platform reset. Intel has not observed this erratum with commercially
available software and has only observed this in a synthetic test environment.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
40
Specification Update
Hide quick links:
Advertisement
Table of Contents
