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AAN61.
Memory Intensive Workloads with Core C6 Transitions May Cause
System Hang
Problem:
Under a complex set of internal conditions, a system running a high cache stress and I/
O workload combined with the presence of frequent core C6 transitions may result in a
system hang.
Implication:
Due to this erratum, the system may hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN62.
Corrected Errors With a Yellow Error Indication May be Overwritten by
Other Corrected Errors
Problem:
A corrected cache hierarchy data or tag error that is reported with
IA32_MCi_STATUS.MCACOD (bits [15:0]) with value of 000x_0001_xxxx_xx01 (where
x stands for zero or one) and a yellow threshold-based error status indication (bits
[54:53] equal to 10B) may be overwritten by a corrected error with a no tracking
indication (00B) or green indication (01B).
Implication:
Corrected errors with a yellow threshold-based error status indication may be
overwritten by a corrected error without a yellow indication.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN63.
PSI# Signal May Incorrectly be Left Asserted
Problem:
When some of the cores in the processor are in C3/C6 state, the PSI# (Power Status
Indicator) signal may incorrectly be left asserted when another core makes a frequency
change request without changing the operating voltage. Since this erratum results in a
possible maximum core current greater than the PSI# threshold of 15A, PSI# should
have been de-asserted.
Implication:
Due to this erratum, platform voltage regulator tolerances may be exceeded and a
subsequent system reset may occur.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
Implication:
AAN64.
Performance Monitor Events DCACHE_CACHE_LD and
DCACHE_CACHE_ST May Overcount
Problem:
The performance monitor events DCACHE_CACHE_LD (Event 40H) and
DCACHE_CACHE_ST (Event 41H) count cacheable loads and stores that hit the L1
cache. Due to this erratum, in addition to counting the completed loads and stores, the
counter will incorrectly count speculative loads and stores that were aborted prior to
completion.
Implication:
The performance monitor events DCACHE_CACHE_LD and DCACHE_CACHE_ST may
reflect a count higher than the actual number of events.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
36
Specification Update
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