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Signal Description
6.8
JTAG/ITP Signals
Table 6-10. JTAG/ITP
Signal Name
BPM#[7:0]
DBR#
PRDY#
PREQ#
TCK
TDI
TDI_M
TDO
TDO_M
TMS
TRST#
Datasheet, Volume 1
Description
Breakpoint and Performance Monitor Signals: Outputs
from the processor that indicate the status of
breakpoints and programmable counters used for
monitoring processor performance.
DBR# is used only in systems where no debug port is
implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can
drive system reset.
PRDY# is a processor output used by debug tools to
determine processor debug readiness.
PREQ# is used by debug tools to request debug
operation of the processor.
TCK (Test Clock) provides the clock input for the
processor Test Bus (also known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the
processor. TDI provides the serial input needed for JTAG
specification support.
TDI_M (Test Data In) transfers serial test data into the
processor. TDI_M provides the serial input needed for
JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the
processor. TDO provides the serial output needed for
JTAG specification support.
TDO_M (Test Data Out) transfers serial test data out of
the processor. TDO_M provides the serial output needed
for JTAG specification support.
TMS (Test Mode Select) is a JTAG specification support
signal used by debug tools.
TRST# (Test Reset) resets the Test Access Port (TAP)
logic. TRST# must be driven low during power on Reset.
Direction
Type
I/O
GTL
O
Asynch
O
GTL
Asynch
I
GTL
I
TAP
I
TAP
I
TAP
O
TAP
O
TAP
I
TAP
I
TAP
55
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