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3.1.3
3.1.4
3.1.5
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3.2
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3.3
Hyper-Threading Technology .....................................................................34
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3.4
Turbo Boost Technology ............................................................................34
4
Power Management .................................................................................................35
4.1
ACPI States Supported .......................................................................................35
4.1.1
System States........................................................................................35
4.1.2
Processor Core/Package Idle States...........................................................35
4.1.3
Integrated Memory Controller States .........................................................35
4.1.4
PCI Express* Link States .........................................................................36
4.1.5
Interface State Combinations ...................................................................36
4.2
Processor Core Power Management ......................................................................36
4.2.1
4.2.2
Low-Power Idle States.............................................................................37
4.2.3
Requesting Low-Power Idle States ............................................................39
4.2.4
Core C-states .........................................................................................39
4.2.4.1
4.2.4.2
4.2.4.3
4.2.4.4
4.2.4.5
4.2.5
Package C-States ...................................................................................41
4.2.5.1
4.2.5.2
4.2.5.3
4.2.5.4
4.3
IMC Power Management .....................................................................................43
4.3.1
Disabling Unused System Memory Outputs.................................................43
4.3.2
DRAM Power Management and Initialization ...............................................44
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.4
PCI Express* Power Management ........................................................................45
5
Thermal Management ..............................................................................................47
6
Signal Description ....................................................................................................49
6.1
System Memory Interface ...................................................................................50
6.2
Memory Reference and Compensation ..................................................................52
6.3
Reset and Miscellaneous Signals ..........................................................................52
6.4
PCI Express* Based Interface Signals ...................................................................53
6.5
DMI-Processor to PCH Serial Interface.................................................................53
6.6
PLL Signals .......................................................................................................54
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6.7
Flexible Display Interface Signals ...............................................................54
6.8
JTAG/ITP Signals ...............................................................................................55
6.9
Error and Thermal Protection...............................................................................56
6.10
Power Sequencing .............................................................................................57
6.11
Processor Core Power Signals ..............................................................................57
6.12
Graphics and Memory Core Power Signals .............................................................59
6.13
Ground and NCTF ..............................................................................................60
6.14
Processor Internal Pull Up/Pull Down ....................................................................60
4
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VT-d Objectives ............................................................................32
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VT-d Features ...............................................................................32
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VT-d Features Not Supported..........................................................33
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Core C0 State ...........................................................................40
Core C1/C1E State ....................................................................40
Core C3 State ...........................................................................40
Core C6 State ...........................................................................40
C-State Auto-Demotion ..............................................................40
Package C0 ..............................................................................42
Package C1/C1E........................................................................42
Package C3 State ......................................................................43
Package C6 State ......................................................................43
Initialization Role of CKE ............................................................44
Conditional Self-Refresh .............................................................44
Dynamic Power Down Operation..................................................44
DRAM I/O Power Management ....................................................45
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TXT) .................................................33
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Technology ..................................................37
Datasheet, Volume 1
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