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7.3
Processor Clocking (BCLK[0], BCLK#[0])
The processor uses a differential clock to generate the processor core(s) operating
frequency, memory controller frequency, and other internal clocks. The processor core
frequency is determined by multiplying the processor core ratio by 133 MHz. Clock
multiplying within the processor is provided by an internal phase locked loop (PLL) that
requires a constant frequency input, with exceptions for Spread Spectrum Clocking
(SSC).
The processor maximum core frequency is configured during power-on reset by using
its manufacturing default value. This value is the highest core multiplier at which the
processor can operate. If lower maximum speeds are desired, the appropriate ratio can
be configured using the FLEX_RATIO MSR.
7.3.1
PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to
specifications.
7.4
V
Voltage Identification (VID)
CC
The VID specification for the processor is defined by the Voltage Regulator Down (VRD)
11.1 Design Guidelines. The processor uses eight voltage identification signals,
VID[7:0], to support automatic selection of voltages.
level corresponding to the state of VID[7:0]. A '1' in this table refers to a high voltage
level and a '0' refers to a low voltage level. If the processor socket is empty (VID[7:0]
= 11111111), or the voltage regulation circuit cannot supply the voltage that is
requested, the voltage regulator must disable itself. See the Voltage Regulator Down
(VRD) 11.1 Design Guidelines for further details. VID signals are CMOS push/pull
drivers. Refer to
change due to temperature and/or current load changes to minimize the power of the
part. A voltage range is provided in
voltage regulator can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in
transitioning to an adjacent VID and its associated processor core voltage (V
will represent a DC shift in the loadline.
Note:
A low-to-high or high-to-low voltage state change will result in as many VID transitions
as necessary to reach the target core voltage. Transitions above the maximum
specified VID are not permitted. One VID transition occurs in 1.25 us.
includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be
maintained.
The VR used must be capable of regulating its output to the value defined by the new
VID values issued. DC specifications for dynamic VID transitions are included in
Table 7-5
for further details.
Several of the VID signals (VID[5:3]/CSC[2:0] and VID[2:0]/MSID[2:0]) serve a dual
purpose and are sampled during reset. Refer to the signal description table in
Chapter 6
62
Table 7-9
for the DC specifications for these signals. The VID codes will
Table
7-5. The processor provides the ability to operate while
and
Table
7-7. See the Voltage Regulator Down (VRD) 11.1 Design Guidelines
and
Table 7-3
for further information.
Table 7-1
Table
7-5. The specifications are set so that one
Electrical Specifications
Table 7-6
for DC
specifies the voltage
). This
CC
Table 7-1
Datasheet, Volume 1
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