Pci Express® Differential Clock Ac Specifications; Power Rail Power-Up Sequence; Figure 4-1 Rx881 Power Rail Power-Up Sequence; Table 4-3 Rx881 Power Rail Power-Up Sequence - AMD RX881 Data Book

®
4.3 PCI Express Differential Clock AC Specifications
Table 4-2 PCI Express
Symbol
Rising Edge Rate
Falling Edge Rate
T
PERIOD AVG
T
PERIOD ABS
T
CCJITTER
Duty Cycle
Rise-Fall Matching
4.4

Power Rail Power-up Sequence

3.3V Rail
(AVDD, VDD33)
1.8V PLL and IO
Transform Rail
(PLLVDD18, IOPLLVDD18, VDDA18HTPLL,
VDDA18PCIEPLL, AVDDDI, AVDDQ, VDD18)
1.1V Rail
(PLLVDD, IOPLLVDD)
1.1V VDDC
Note: There are no specific requirements for the following 1.1V or 1.2V rails: VDDHT, VDDHTRX, VDDHTTX, VDDPCIE

Table 4-3 RX881 Power Rail Power-up Sequence

Symbol
3.3-V rail ramps high relative to 1.8-V PLL and IO
T11
transform rails
1.8-V PLL and IO transform rails ramp high relative
T12
to 1.1-V rail (PLLVDD, IOPLLVDD)
1.1-V rail (PLLVDD, IOPLLVDD) ramps high relative
T13
to VDDC (1.1V)
46136 AMD RX881 Databook 1.40
4-2
®
Differential Clock (GFX_REFCLK, GPPSB_REFCLK, 100MHz) AC Characteristics
Description
Rising Edge Rate
Falling Edge Rate
Average Clock Period Aquaria
Absolute Period (including jitter and spread spectrum
modulation)
Cycle to Cycle Jitter
Duty Cycle
Rising edge rate (REFCLK+) to falling edge rate
(REFCLK-) matching
T11

Figure 4-1 RX881 Power Rail Power-up Sequence

Parameter
PCI Express® Differential Clock AC Specifications
Minimum
0.6
0.6
-300
9.847
-
40
-
T12
T13
Voltage Difference During Ramping
Minimum (V)
0
0
0
© 2011 Advanced Micro Devices, Inc.
Maximum Unit
4.0 V/ns
4.0 V/ns
+2800 ppm
10.203 ns
150 Ps
60 %
20 %
Maximum (V)
2.1
No restrictions
No restrictions
Proprietary