Phy Layer Control Register; Phy Control Register Description - Texas Instruments PCI7621 Data Manual

8.33 PHY Layer Control Register

The PHY layer control register reads from or writes to a PHY register. See Table 8−25 for a complete description of
the register contents.
Bit 31 30 29
Name
Type RU R R
Default 0 0
Bit 15 14 13
Name
Type RWU RWU R
Default 0 0
Register: PHY layer control
Offset: ECh
Type: Read/Write/Update, Read/Write, Read/Update, Read-only
Default: 0000 0000h
BIT FIELD NAME
31 rdDone
30−28 RSVD
27−24 rdAddr
23−16 rdData
15 rdReg
14 wrReg
13−12 RSVD
11−8 regAddr
7−0 wrData
8−30
28 27 26 25
R RU RU RU
0 0 0 0 0
12 11 10 9
R RW RW RW
0 0 0 0 0
Table 8−25. PHY Control Register Description
TYPE
RU Bit 31 is cleared to 0 by the PCI7x21/PCI7x11 controller when either bit 15 (rdReg) or bit 14 (wrReg)
is set to 1. This bit is set to 1 when a register transfer is received from the PHY layer.
R Reserved. Bits 30−28 return 0s when read.
RU This field is the address of the register most recently received from the PHY layer.
RU This field is the contents of a PHY register that has been read.
RWU Bit 15 is set to 1 by software to initiate a read request to a PHY register, and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1
simultaneously.
RWU Bit 14 is set to 1 by software to initiate a write request to a PHY register, and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1
simultaneously.
R Reserved. Bits 13 and 12 return 0s when read.
RW This field is the address of the PHY register to be written or read. The default value for this field is 0h.
RW This field is the data to be written to a PHY register and is ignored for reads. The default value for this
field is 00h.
24 23 22 21
PHY layer control
RU RU RU RU
0 0 0 0
8 7 6 5
PHY layer control
RW RW RW RW
0 0 0 0
DESCRIPTION
20 19 18 17
RU RU RU RU
0 0 0 0
4 3 2 1
RW RW RW RW
0 0 0 0
16
RU
0
0
RW
0