Texas Instruments MSP50C614 User Manual

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MSP50C614

Mixed-Signal Processor

User's Guide

SPSU014

January 2000

Printed on Recycled Paper

Table of Contents

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Table of Contents

Summary of Contents for Texas Instruments MSP50C614

Page 1 MSP50C614 Mixed-Signal Processor User’s Guide SPSU014 January 2000 Printed on Recycled Paper...
Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
Page 3: Read This First
Preface Read This First About This Manual This user’s guide gives information for the MSP50C61 mixed-signal proces- sor. This information includes a functional overview, a detailed architectural description, device peripheral functional description, assembly language instruction listing, code development tools, applications, customer informa- tion, and electrical characteristics (in data sheet).
Page 4 Notational Conventions version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing: 0011 0005 0001...
Page 5 Information About Cautions and Warnings Unless the list is enclosed in square brackets, you must choose one item from the list. Some directives can have a varying number of parameters. For example, the .byte directive can have up to 100 parameters. The syntax for this di- rective is: .byte value [, ...
Page 7: Table Of Contents
Contents Contents Introduction to the MSP50C614 ........... Features of the C614 .
Page 8 Contents 3.1.1 General-Purpose I/O Ports ..........3.1.2 Dedicated Input Port F .
Page 9 Contents 4.4.8 Class 8 Instructions: Logic and Bit ........4-41 4.4.9 Class 9 Instructions: Miscellaneous...
Page 10 ............Texas Instruments C614 Synthesis Code .
Page 11 Contents B.3.5 Host Write Sequence ..........B.3.6 Host Read Sequence .
Page 12 Figures Figures 1–1 Functional Block Diagram for the C614 ......... . 1–2 Oscillator and PLL Connection .
Page 13 Figures 5–9 Select Program Folder Dialog ..........5-10 5–10 Copying Files...
Page 14 Tables Tables 1–1 Signal and Pad Descriptions for the C614 ........1-10 1–2 MSP50C614 100-Pin PJM Plastic Package Pinout Description...
Page 15 Tables 4–25 Class 4d Instruction Description ..........4-35 4–26 Class 5 Instruction Encoding...
Page 16 Notes, Cautions, and Warnings Notes, Cautions, and Warnings MSP50C605 and MSP50C604 ............PGA Package .
Page 17: Introduction To The Msp50C614
Chapter 1 Introduction to the MSP50C614 The MSP50C614 (C614) is a low cost, mixed signal controller, that combines a speech synthesizer, general-purpose I/O, onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new DSP which gives the C614 unprecedented speed and computational flexibility compared with previous devices of its type.
Page 18: Features Of The C614
Features of the C614 1.1 Features of the C614 Advanced, integrated speech synthesizer for high quality sound Operates up to 8 MHz (performs up to 8 MIPS) Very low-power operation, ideal for hand-held devices Low voltage operation, sustainable by three batteries Reduced power stand-by modes, less than 10 A in deep-sleep mode Supports high-quality synthesis algorithms such as MELP, CELP, LPC, and ADPCM...
Page 19: Applications
Applications 1.2 Applications Due to its low cost, low-power needs, and high programmability, the C614 is suitable for a wide variety of applications incorporating I/O control and high- quality speech: Talking Toys Talking Books Electronic Learning Aids Talking Dictionaries Games Warning Systems Talking Clocks Equipment for the Handicapped...
Page 20: Development Device: Msp50P614
Development Device: MSP50P614 1.3 Development Device: MSP50P614 The MSP50P614 is an EPROM based version of the MSP50C614, and is available in 120 pin windowed ceramic pin grid array. This EPROM based version of the device is only available in limited quantities to support software development.
Page 21: Functional Description
32K 17-bit words. The total ROM space is divided into two areas: 1) The lower 2K words are re- served by Texas Instruments for a built-in self-test, 2) the upper 30K is for user program/data. The data memory is internal static RAM. The RAM is configured in 640 17-bit words.
Page 22: C605 And C604 (Preliminary Information)
C605 and C604 (Preliminary Information) built in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The block diagram appearing in Figure 1–1 gives an overview of the C614 functionality. IMPORTANT: a one bit comparator is not currently supported. Typical connections to implement reset functionality are shown in Figure 1–3. 1.5 C605 and C604 (Preliminary Information) Two related products, the MSP50C605 (C605) and MSP50C604(C604) use the C614 core.
Page 23: Functional Block Diagram For The C614
C605 and C604 (Preliminary Information) Figure 1–1. Functional Block Diagram for the C614 V SS V DD V PP Power (P614 only) A port I/O Scan Interface SCAN IN PA 0–7 Data 0x00 (EP)ROM 32k x (16 + 1) bit Control 0x04 Break Point...
Page 24: Oscillator And Pll Connection
C605 and C604 (Preliminary Information) Figure 1–2. Oscillator and PLL Connection a) Crystal Oscillator Operation Connections MSP50P614 MSP50C614 OSC IN OSCOUT 10 M † 32.768 kHz† 10 M † 22 pF† 22 pF† C (PLL) = 3300 pF† † Keep these components as close as possible to the OSC IN , OSC OUT , and PLL pins. b) Resistor Trim Operation Connections MSP50C614 MSP50P614...
Page 25: Reset Circuit
C605 and C604 (Preliminary Information) Figure 1–3. RESET Circuit To Pin 1 of Optional (Scanport) (MSP50P614 only) Connector IN914 ‡ V PP V DD IN914 100 k 1 k † RESET Inside the MSP50P614 MSP50C614 Reset (20%) Switch To Pin 2 of optional (scan port) connector † V SS †...
Page 26: Terminal Assignments And Signal Descriptions
Terminal Assignments and Signal Descriptions 1.6 Terminal Assignments and Signal Descriptions Table 1–1. Signal and Pad Descriptions for the C614 SIGNAL PAD NUMBER DESCRIPTION Input/Output Ports PA 0 – PA 7 Port A general-purpose I/O (1 Byte) PB 0 – PB 7 Port B general-purpose I/O (1 Byte) PC 0 –...
Page 27: Msp50C614 100-Pin Pjm Plastic Package Pinout Description
Terminal Assignments and Signal Descriptions The C614 is sold in die form for its volume production. Contact you local TI sales office for mount and bond information. MSP50C614 is also available in 100 pin plastic QFP package. The pinout is shown in Figure 1–4 and Table 1–2.
Page 28: Msp50C614 100 Pin Pjm Plastic Package Pinout
Terminal Assignments and Signal Descriptions Figure 1–4. MSP50C614 100 Pin PJM PLastic Package Pinout (Preliminary Information) PJM PACKAGE (TOP VIEW) GND3/DA DACM 3/DA DACP GND1 PG15 PG14 PG13 PG12 PG11 PG10 GND4 1-12...
Page 29: Pin Grid Array Package For The Development Device, P614
Terminal Assignments and Signal Descriptions For software development and prototyping, a windowed ceramic 120-pin grid array packaged P614 is available. The P614’s PGA package is shown in Figure 1–5 and Table 1–3: Figure 1–5. 120 Pin Grid Array Package for the Development Device, P614 MSP50P614 extra pin 12 11...
Page 30 Terminal Assignments and Signal Descriptions The pin assignments for the 120-pin PGA package (P614 device only) are out- lined in the following table. Refer to Section 1.6 for more information on the signal functions. V DD † PF 7 PF 5 PF 2 V PP PG 15...
Page 31: Msp50C614 Architecture
Chapter 2 MSP50C614 Architecture A detailed description of MSP50C614 architecture is included in this chapter. After reading this chapter, the reader will have in-depth knowledge of internal blocks, memory organization, interrupt system, timers, clock control mecha- nism, and various low power modes. Topic Page Architecture Overview...
Page 32: Architecture Overview
2.1 Architecture Overview The core processor in the C614 is a medium performance mixed signal pro- cessor with enhanced microcontroller features and a limited DSP instruction set. In addition to its basic multiply/accumulate structure for DSP routines, the core provides for a very efficient handling of string and bit manipulation. A unique accumulator-register file provides additional scratch pad memory and minimizes memory thrashing for many operations.
Page 33: Msp50C614 Core Processor Block Diagram
Figure 2–1. MSP50C614 Core Processor Block Diagram Interrupt Inputs Peripheral Interface Interrupt Flag Register (IFR)† Multiplier (MR)† Shift Value (SV)† Control Register (CTRL)† Interrupt Processor 17 x 17 Multiplier Serial Serial Interface Register† Interface Oscillator Register† Product High (PH)† Timer Period (PRD1 and PRD2)† Timer Register (TIM1 and TIM2)†...
Page 34: Computational Unit Block Diagram
Figure 2–2. Computational Unit Block Diagram (The shaded boxes represent internal programmable registers.) Shift Value (SV) Multiplier Register (MR) 17 bit x 17 bit (Product Low, PL) Multiplexer 16 LSB 16 MSB Product High (PH) Read/Write Accumulators AC16 AC17 AC18 AC19 AC20 AC21...
Page 35: Computation Unit
Computation Unit 2.2 Computation Unit The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’s algorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagram of the CU is shown in Figure 2–2. The multiplier block is served by 4 system registers: a 16-bit multiplier register (MR), a 16-bit write-only multiplicand register, a 16-bit high word product register (PH), and a 4-bit shift value register (SV).
Page 36 Computation Unit The multiplicand source can be either data memory, an accumulator, or an accumulator offset. The multiplier source can be either the 16-bit multiplier register (MR) or the 4-bit shift value (SV) register. For all multiply operations, the MR register stores the multiplier operand. For barrel shift instructions, the multiplier operand is a 4-to-16-bit value that is decoded from the 4-bit shift value register (SV).
Page 37: Arithmetic Logic Unit
Computation Unit Figure 2–3. Overview of the Multiplier Unit Operation MULTIPLIER UNIT INPUTS Multiplicand 16-bit Multiplier - latched in a write-only register - writeable and readable by Data Memory from one of the following sources ... as one of the following ... MULTIPLYING: (MR) Multiplier Register†...
Page 38 Computation Unit The all-zero values are necessary for data transfers and unitary operations. All-zeros also serve as default values for the registers, which helps to minimize residual power consumption. The databus path through ALU-A is used to input memory values (RAM) and constant values (program memory) to the ALU. The PH and PL inputs are useful for supporting multiply-accumulate operations (refer to Section 2.2.1, Multiplier ).
Page 39: Overview Of The Arithmetic Logic Unit
Computation Unit Figure 2–4. Overview of the Arithmetic Logic Unit ALU INPUTS ALU-A 16-bit ALU-B 16-bit - selects between ... - selects between ... all 0’s all 0’s Offset Accumulator Register Accumulator Register Data Memory Program Memory (PH) Product High† (PL) Product Low†...
Page 40: Overview Of The Arithmetic Logic Unit
Computation Unit When writing an accumulator-referenced instruction, therefore, the working accumulator address is stored in one of AP0 to AP3. The C614 instruction set provides a two-bit field for all accumulator referenced instructions. The two-bit field serves as a reference to the accumulator pointer which, in turn, stores the address of the actual 16-bit accumulator.
Page 41: Data Memory Address Unit
Data Memory Address Unit For some instructions, the 5-bit string processor can also preincrement or predecrement the AP pointer-value by +1 or –1, before being used by the accumulator register block. This utility can be effectively used to minimize software overhead in manipulating the accumulator address. The premodification of the address avoids the software pipelining effect that post-modification would cause.
Page 42: Ram Configuration
Data Memory Address Unit Figure 2–6. Data Memory Address Unit Arithmetic Block RAM Address LOOP INDEX PAGE STACK Register Addressing Mode Internal Databus Internal Program Bus 2.3.1 RAM Configuration The data memory block (RAM) is physically organized into 17-bit parallel words.
Page 43: Data Memory Addressing Modes
Data Memory Address Unit There are two-byte instructions, for example MOVB, which cause the proces- sor to read or write data in a byte (8-bit) format. (The B appearing at the end of MOVB designates it as an instruction, which uses byte-addressable argu- ments.) The byte-addressable mode causes the hardware to read/write either the upper or lower 8 bits of the 16-bit word based on the LSB of the address.
Page 44: Interrupt Service Branch
Program Counter Unit 2.4 Program Counter Unit The program counter unit provides addressing for program memory (onboard ROM). It includes a 16-bit arithmetic block for incrementing and loading addresses. It also consists of the program counter (PC), the data pointer (DP), a buffer register, a code protection write-only register, and a hardware loop counter (for strings and repeated-instruction loops).
Page 45: Memory Organization: Ram And Rom
Memory Organization: RAM and ROM 2.6 Memory Organization: RAM and ROM Data memory (RAM) and program memory (ROM) are each restricted to internal blocks on the C614. The program memory is read-only and limited to 32K, 17-bit words. The lower 2048 of these words is reserved for an internal test code and is not available to the user.
Page 46: C614 Memory Map (Not Drawn To Scale)
Memory Organization: RAM and ROM Figure 2–7. C614 Memory Map (not drawn to scale) Data Memory Peripheral Ports Program Memory 0x0000 0x0000 0x00 PA 0–7 data Internal Test Code 2048 x 17 bit 640 x 17 bit 0x04 PA 0–7 ctrl 0x027F 0x08 PB 0–7 data...
Page 47: Summary Of C614'S Peripheral Communications Ports
Memory Organization: RAM and ROM When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend as far as width of location. Within a 16-bit accumulator, the desired bits (width of location) should be right-justified. The write operation is accomplished using the OUT instruction, with the address of the I/O port as an argument.
Page 48: Rom Locations That Hold Interrupt Vectors
Memory Organization: RAM and ROM Table 2–2. Summary of C614’s Peripheral Communications Ports (Continued) I/O Map Width of Allowable State after Section for Control Register Name Abbreviation Address Location Access RESET LOW Reference 0x3A 16 bits read & write TIMER1 period PRD1 0x0000 0x3B...
Page 49: Rom Code Security
Memory Organization: RAM and ROM 3.1.5, Internal and External Interrupts , for more information regarding the specific conditions for each interrupt-trigger event. The branch operation, however, is also contingent on whether the interrupt service has been enabled. This is done individually for each interrupt, using the interrupt mask bits within the interrupt/general control register.
Page 50 Memory Organization: RAM and ROM The protection modes are implemented on the C614 as follows. Within the ROM is a dedicated storage for the block protection word (address 0x7FFE). The block protection word is divided into two 6-bit fields and two single-bit fields.
Page 51 Memory Organization: RAM and ROM + 1) * 512 – 1] = highest ROM address within the block to be protected + 1) * 512 = lowest ROM address which is left unprotected = the value programmed at TM5 TM0 (true protection marker) the binary complement of N = the value programmed at FM5 FM0 (false...
Page 52: Macro Call Vectors
Interrupt Logic When the device is powered up, the hardware initialization circuit reads the value stored in the block protection word. The value is then loaded to an inter- nal register and the security state of the ROM is identified. Until this occurs, execution of any instructions is suspended.
Page 53 Interrupt Logic the RESET low, assuming there is no interruption in power. For a full description of the interrupt-trigger events, refer to Section 3.1.5, Internal and External Interrupts . (8-bit wide location) INT number Interrupt Flag register D4 PF address 0x39 high priority priority...
Page 54 Interrupt Logic Note: Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtain- ing a software interrupt. An IFR bit may also be cleared, using OUT, at any time.
Page 55: Interrupt Initialization Sequence
Interrupt Logic Figure 2–8 provides an overview of the interrupt control sequence. INT0 is the highest priority interrupt, and INT7 is the lowest priority interrupt. Figure 2–8. Interrupt Initialization Sequence CLEAR INTD instruction Global Interrupt Enable INTE CLEAR instruction Interrupt-Trigger Event Internal Timer Underflow External Input Falling-Edge External Input Rising-Edge...
Page 56: Timer Registers
Timer Registers In addition to being individually enabled, all interrupts must be GLOBALLY enabled before any one can be serviced. Whenever interrupts are globally disabled, the interrupt flag register may still receive updates on pending trigger events. Those trigger events, however, are not serviced until the next INTE instruction is encountered.
Page 57: Writing To The Tim Register
Timer Registers (16-bit wide location) † PRD1 register address 0x3A TIMER1 Period † TIM1 register address 0x3B TIMER1 Count-Down Triggers INT1 on underflow PRD2 register address 0x3E TIMER2 Period TIM2 register address 0x3F TIMER2 Count-Down Triggers INT2 on underflow P : period register (initial counter value) T : count-down register (counts from the value in P) 0x0000 : default state of both registers after RESET LOW †...
Page 58 Timer Registers Selection between the timer-source options is made using two control bits in the interrupt/general control register (IntGenCtrl). The IntGenCtrl is a 16-bit port-addressed register at 0x38. Clearing bit 8 selects 1/2 MC as the source for TIMER1. Setting bit 8 selects the reference oscillator as the source for TIM- ER1.
Page 59: Clock Control
Clock Control 2.9 Clock Control 2.9.1 Oscillator Options The C614 has two oscillator options available. Either option may be enabled using the appropriate control bits in the clock speed control register (ClkSpdCtrl). The ClkSpdCtrl is described in Section 2.9.3, Clock Speed Con- trol Register .
Page 60: Clock Speed Control Register
Clock Control The maximum required CPU clock frequency for the C614 is 8 MHz over the entire V range. This rate applies to the speed of the core processor. Higher CPU clock frequencies may be achieved, but these are not qualified over the complete range of supply voltages in the guaranteed specification.
Page 61 Clock Control Note: ClkSpdCtrl Bits 8 and 9 When bit 8 is set in the ClkSpdCtrl register, the crystal oscillator bit (bit 9) be- comes the least significant bit of the 6-bit resistor trim value. Thus, bits 15–11 and 9 make up the 6-bit resistor trim value. For example, if the ClkSpdCtrl register is 00010X11XXXXXXXX (X means don’t care, bold numbers are re- sistor trim bits), then the resistor trim value is equal to five.
Page 62: Rto Oscillator Trim Adjustment
(17-bit wide location) T5 T4 T3 T2 T: RTO oscillator-trim storage (device specific) R: reserved for Texas Instruments use ClkSpdCtrl Value Copied (Shaded) M7 M6 M5 M4 M3 M2 M1 M0 When selecting and enabling the RTO oscillator,therefore, the bits at positions...
Page 63: Execution Timing
Execution Timing However, the general specification of the adjustment can be useful in certain circumstances. For example, the adjustment can be used to obtain a program- matic increase or decrease in the speed of the RTO reference. The default val- ue for the adjustment, after RESET low, is all zeros.
Page 64: Instruction Execution And Timing
Reduced Power Modes Figure 2–10. Instruction Execution and Timing CLOCK FETCH DECODE N–1 EXEC N–1 N–2 DATA ADD N–1 PC ADD 2.11 Reduced Power Modes The power consumption of the C614 is greatest when the DAC circuitry is called into operation, i.e., when the synthesizer speaks. There are, however, a number of reduced power modes (sleep states) on the C614 which may be engaged during quiet intervals.
Page 65 Reduced Power Modes The deepest sleep achievable on the C614, for example, is a mode where all of the previously listed subsytems are stopped. In this state, the device draws less than 10 A of current and obtains the greatest power savings. It may be awakened from this state using an external interrupt (input port).
Page 66 Reduced Power Modes The power consumed during sleep when the RTO oscillator is left running is greater than the power consumed during sleep when the CRO oscillator is left running. If the idle state clock control is clear, then the PLL circuitry, active during sleep, will attempt to regulate the MC to whatever frequency is programmed in the PLL multiplier (see Section 2.9.3, Clock Speed Control Register ).
Page 67: Programmable Bits Needed To Control Reduced Power Modes
Reduced Power Modes Table 2–3. Programmable Bits Needed to Control Reduced Power Modes deeper sleep relatively less power Label for Control Bit LIGHT DEEP Control Bit Idle state clock control bit 10 ClkSpdCtrl register (0x3D) Enable reference oscillator bit 09 : CRO or bit 08 : RTO ClkSpdCtrl register (0x3D) bit 14...
Page 68: Status Of Circuitry When In Reduced Power Modes
Reduced Power Modes Table 2–4. Status of Circuitry When in Reduced Power Modes (Refer to Table 2–3) deeper sleep relatively less power Determined Component LIGHT DEEP by Controls CPU clock stopped stopped stopped (processor core) PLL clock circuitry A, E running stopped stopped...
Page 69: How To Wake-Up From Reduced Power Modes
Reduced Power Modes The interrupt-trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER. In order for a TIMER underflow to occur during sleep, the TIMER must be left running before going to sleep. In certain cases, however, the act of going to sleep can bring a TIMER to stop, thereby preventing a TIMER-induced wake-up.
Page 70: Destination Of Program Counter On Wake-Up Under Various Conditions
Reduced Power Modes In order to wake the device using a programmable interrupt, the interrupt mask register must have the respective bit set to enable interrupt service (see Sec- tion 2.7, Interrupt Logic ). In some cases, the ARM bit must also be set, in order for the interrupts to be visible during sleep Table 2–3.
Page 71: Peripheral Functions
Chapter 3 Peripheral Functions This chapter describes in detail the MSP50C614 peripheral function, i.e., I/O control ports, general purpose I/O ports, interrupt control registers, compara- tor and digital-to-analog (DAC) control mechanisms. Topic Page I/O ............3–2 Digital-to-Analog Converter (DAC) .
Page 72: General-Purpose I/O Ports
3.1 I/O The C614 has 64 input-output pins. Forty of these are software configurable as either inputs or outputs. Eight are dedicated inputs, and the remaining sixteen are dedicated outputs. 3.1.1 General-Purpose I/O Ports The forty configurable input/output pins are organized in 5 ports, A,B,C,D, and E.
Page 73 is 0x00 (all inputs). The state of the data registers after RESET low is unknown (input state provided by external hardware). The 8-bit width is the true size of the mapped location. This is independent of the address spacing, which is greater than 8-bits. When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend across 8 bits.
Page 74: Dedicated Input Port F
3.1.2 Dedicated Input Port F Port F is an 8-bit wide input-only port. The data presented to the input pin can be read by referring to the appropriate bit in the F port data register, address 0x28. This is done using the IN instruction, with the 0x28 address as an argument.
Page 75: Dedicated Output Port G
3.1.3 Dedicated Output Port G Port G is a 16-bit wide output-only port. The output drivers have a Totem-Pole configuration. The data driven by the output pin can be controlled by setting or clearing the appropriate bit in the G port Data register, address 0x2C. This is done using the OUT instruction, with the 0x2C address as an argument.
Page 76: Branch On D Port
3.1.4 Branch on D Port Instructions exist to branch conditionally depending upon the state of ports D and D . These conditionals are COND1 and COND2, respectively. The condi- tionals are supported whether the D and D ports are configured as inputs or as outputs.
Page 77 Registers ). INT1 and INT2 are high-priority, internal interrupts triggered by the underflow conditions on TIMER1 and TIMER2, respectively. Please refer to Section 2.8, Timer Registers , for a full description of the TIMER controls and their underflow conditions. When properly enabled, any of these interrupts may be used to wake the de- vice up from a reduced-power state.
Page 78: Digital-To-Analog Converter (Dac)
Digital-to-Analog Converter (DAC) 3.2 Digital-to-Analog Converter (DAC) The C614 incorporates a two-pin pulse-density-modulated DAC which is capable of driving a 32 loudspeaker directly. To drive loud speakers other than 32 , an external impedance-matching circuit is required. 3.2.1 Pulse-Density Modulation Rate The rate of the master clock (MC) determines the pulse-density-modulation (PDM) rate, and this governs the output sampling-rate and the achievable DAC resolution.
Page 79 Digital-to-Analog Converter (DAC) DAC Control register Address 0x34 (4-bit wide location) Set DAC resolution to 8 bits: Set DAC resolution to 9 bits: Set DAC resolution to 10 bits: DM : Drive Mode selection (0 = C3x style : 1 = C5x style) E : pulse-density-modulation Enable (overall DAC enable) 0x0 : default state of register after RESET low Bit 2 in the DAC control register is used to enable/disable the pulse-density...
Page 80: Pdm Clock Divider
Digital-to-Analog Converter (DAC) style . Their selection is made at bit 3 of the DAC control register (0x34). The C3x style is selected by clearing bit 3, and the C5x style is selected by setting bit 3. The default value of the selection is zero which yields the C3x style . The overflow bits appear in the DAC data register (14 and 13) to the left of the MSB data bit (12).
Page 81 This rate applies to the speed of the core processor. Operating the processor higher than the listed specification is not recommended by Texas Instruments. The following tables illustrate a number of possible combinations with respect to sampling rate, PDM rate, DAC resolution, master clock rate, and CPU clock rate.
Page 82 Digital-to-Analog Converter (DAC) 8 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference ClkSpdCtrl Number of Number of PLLM Master Output Instructs Instructs Register Between Between IntGenCtrl Over- Clock Clock Sampling PDMCD Sampling Value Rate Rate Rate Rate 8 kHz Precision Factor (hex) (MHz)
Page 83 Digital-to-Analog Converter (DAC) 10 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference ClkSpdCtrl Number of Number of PLLM Master Output Instructs Instructs Register Between Between IntGenCtrl Over- Clock Clock Sampling PDMCD Sampling Value Rate RATE Rate Rate 10 kHz Precision Factor (hex) (MHz)
Page 84: Comparator
Comparator 3.3 Comparator The C614 provides a simple comparator that is enabled by a control register option. The inputs of the comparator are shared with pins PD and PD . PD is the noninverting input to the comparator, and PD is the inverting input.
Page 85: Relationship Between Comparator/Interrupt Activity And The Timer1 Control
Comparator bit is automatically CLEARed again if an INT6 event occurs at the same time that the associated mask bit is SET (IntGenCtrl, address 0x38, bit 6). The latter indicates that the program vectoring associated with INT6 is enabled. (The flag bit is SET when the INT event occurs.
Page 86 Comparator The comparator, along with all of its associated functions, is enabled by setting bit 15 of the interrupt/general control register (IntGenCtrl, address 0x38). The default value of the register is zero: comparator disabled. Note: IntGenCtrl Register Bit 15 At the time that bit 15 in the IntGenCtrl is set, PD and PD become the comparator inputs.
Page 87: Interrupt/General Control Register
Interrupt/General Control Register 3.4 Interrupt/General Control Register The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register located at address 0x38. The primary component in the IntGenCtrl is the 8-bit interrupt mask register (IMR). The service branch enable status for each of the eight interrupts is registered in the IMR.
Page 88 Interrupt/General Control Register The upper four bits in the IntGenCtrl have independent functions. Bit 12 is the enable bit for the pull-up resistors on input port F. Setting this bit engages all 8 F-port pins with at least 100-k pull-ups (see Section 3.1.2, Dedicated Input Port F ) Bit 13 is the PDMCD bit for the pulse-density modulation clock.
Page 89: Hardware Initialization States
Hardware Initialization States 3.5 Hardware Initialization States The RESET pin is configured at all times as an external interrupt. It provides for a hardware initialization of the C614. When the RESET pin is held low, the device assumes a deep sleep state and various control registers are initialized.
Page 90 Hardware Initialization States Note: Internal RAM State after Reset The RESET low will not change the state of the internal RAM, assuming there is no interruption in power. This applies also to the interrupt flag register. The same applies to the states of the accumulators in the computational unit. When RESET is brought back high again, many of the programmable controls and registers are left in their default states: RESET high, just after low .
Page 91: State Of The Status Register (17 Bit) After Reset Low-To-High
Hardware Initialization States Note: Stack Pointer Initialization The software stack pointer (R7) must be initialized by the programmer, so that it points to some legitimate address in data memory (RAM). This must be done prior to any CALL or C instruction.
Page 92 3-22...
Page 93: Assembly Language Instructions
Chapter 4 Assembly Language Instructions This chapter describes in detail about MSP50P614/MSP50C614 assembly language. Instruction classes, addressing modes, instruction encoding and explanation of each instruction is described. Topic Page Introduction ..........4–2 System Registers .
Page 94: Introduction
Introduction 4.1 Introduction In this chapter each MSP50P614/MSP50C614 class of instructions is explained in detail with examples and restrictions. Most instructions can individually address bits, bytes, words or strings of words or bytes. Usable program memory is 30K by 17-bit wide and the entire 17-bits are used for instruction set encoding.
Page 95: Top Of Stack (Tos) Register Operation
System Registers or by 2 for double word instructions) each execution cycle and points to the next program memory location to fetch. During a maskable interrupt, the next PC address is stored in the TOS register and is reloaded from TOS after the interrupt encounters an IRET instruction.
Page 96: Product High Register (Ph)
System Registers It is recommended to avoid using the TOS register altogether in applications and leave its operation to development tools only. 4.2.6 Product High Register (PH) This register holds the upper 16 bits of the 32 bit result of a multiplication, multiply-accumulate, or shift operation.
Page 97: Accumulator Pointers (Ap0–Ap3)
System Registers During accumulator read operations, both A n and offset A n ~ are fetched. Depending on the instruction, either or both registers may be used. In addition, some write operations allow either register to be selected. The accumulator block can also be used in string operations. The selected accumulator (A n or A n ~) is the least significant word (LSW) of the string and is restored at the end of the operation.
Page 98: String Register (Str)
System Registers value of the STACK register should be stored before use and restored after use. This register must point to the beginning of the stack in the RESET initialization routine before any CALL instruction or maskable interrupts can be used.
Page 99 System Registers Table 4–1. Status Register (STAT) Name Function Sign extended mode bit. This bit is one, if sign extension mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. Unsigned multiplier mode. This bit is one if unsigned multiplier mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6.
Page 100: Instruction Syntax And Addressing Modes
Instruction Syntax and Addressing Modes 4.3 Instruction Syntax and Addressing Modes MSP50P614/MSP50C614 instructions can perform multiple operations per instruction. Many instructions may have multiple source arguments. They can premodify register values and can have only one destination. The addressing mode is part of the source and destination arguments. In the following subsec- tion, a detail of the MSP50P614/MSP50C614 instruction syntax is explained followed by the subsection which describes addressing modes.
Page 101: Addressing Mode Encoding
Instruction Syntax and Addressing Modes 4.3.2 Addressing Modes The addressing modes on the MSP50P614/MSP50C614 are immediate, di- rect, indirect with post modification, and three relative modes. The relative modes are: Relative to the INDEX or R5 register. The effective address is (indirect reg- ister + INDEX).
Page 102 Instruction Syntax and Addressing Modes Table 4–3. Rx Bit Description Operation R4 or LOOP R5 or INDEX R6 or PAGE R7 or STACK Table 4–4. Addressing Mode Bits and {adrs} Field Description addressing mode encoding, adrs Relative Relative Repeat Repeat Clocks Words ‡...
Page 103: Msp50P614/Msp50C614 Addressing Modes Summary
Instruction Syntax and Addressing Modes Table 4–5. MSP50P614/MSP50C614 Addressing Modes Summary ADDRESSING SYNTAX OPERATION name [dest,] [src,] *dma16 [*2] [, next A] Second word operand ( dma16 ) used directly as memory Direct name *dma16 [*2] [,src] [, next A] address.
Page 104: Flag Addressing Field {Flagadrs} For Certain Flag Instructions (Class 8A)
Instruction Syntax and Addressing Modes For any particular addressing mode, replace the { adrs } with the syntax shown in Table 4–4. To encode the instruction, replace the am , R x and pm bits with the bits required by the addressing mode (Table 4–4). For example, the instruction indicates all of the following (only partial MOV A n [~], { adrs } [, next A ]...
Page 105: Initial Processor State For The Examples Before Execution Of Instruction
Instruction Syntax and Addressing Modes 4.3.3 Immediate Addressing The address of the memory location is encoded in the instruction word or the word following the opcode is the immediate value. Single word instructions take one clock cycle and double word instructions take two clock cycles. Syntax: name dest , [ src ,] imm [, next A ] Where: imm is the immediate value of a 16 bit number.
Page 106: Direct Addressing
Instruction Syntax and Addressing Modes 4.3.4 Direct Addressing Direct addressing always requires two instruction words. The second word operand is used directly as the memory address. The memory operand may be a label or an expression. Syntax: name [ dest ,] [ src ,] * dma16 [* 2] [, next A ] name * dma16 [* 2] [, src ] [, next A ] Memory Operand Operand...
Page 107: Indirect Addressing Syntax
Instruction Syntax and Addressing Modes 4.3.5 Indirect Addressing Indirect addressing uses one of 8 registers (R0...R7) to point memory addresses. The selected register can be post-modified. Modifications include increments, decrements, or increments by the value in the index register (R5). For post-modifications, the register increments or decrements itself by 2 for word operands and by 1 for byte operands.
Page 108: Relative Addressing
Instruction Syntax and Addressing Modes Example 4.3.12 MOV *R5++R5, A0~, ++A Refer to the initial processor state in Table 4–8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19. The contents of AC19 are stored in the data memory location in R5. R5 is then incremented by R5.
Page 109 Instruction Syntax and Addressing Modes Address (x = 0 – 7) Index Register (R5) Operand Example 4.3.17 AND A0, *R3+R5 Refer to the initial processor state in Table 4–8 before execution of this instruc- tion. A0 is accumulator AC2. The contents of the data memory byte location pointed to by R3+R5 is ANDed with AC2.
Page 110 Instruction Syntax and Addressing Modes Example 4.3.20 MOV A3, *R6+0x10 Refer to the initial processor state in Table 4–8 before execution of this instruc- tion. Load A3 (AC29) with the contents of byte address, R6+0x10. The value of R6 is unchanged. Final result, AC29=0x0112. Example 4.3.21 ADD A0~, A0, *R6+0x10, ++A Refer to the initial processor state in Table 4–8 before execution of this instruc-...
Page 111: Relative Flag Addressing
Instruction Syntax and Addressing Modes 4.3.7 Flag Addressing This addressing mode addresses only the 17 bit (the flag/tag bit) located in data memory. This addressing applies to Class 8a instructions as explained in section 4.4. Using flag addressing, the flag bit can be loaded or saved. In addition, various logical operations can be performed without affecting the re- maining 16 bits of the selected word.
Page 112: Instruction Syntax And Addressing Modes
Instruction Syntax and Addressing Modes 4.3.8 Tag/Flag Bits The words TAG and flag may be used interchangeably in this manual. The TAG bit is the 17 bit of a word of data memory. There are 640 words of RAM, each 17 bits wide, on the C614. Therefore, there are 640 TAG bits on the C614. When an instruction of the format, MOV accumulator, RAM is performed, the STAT register is affected by various properties of this trans-...
Page 113 Instruction Syntax and Addressing Modes However, xFLAG instructions use {flagadrs} addressing modes. This includes global (dma6) and relative (R6 + 6–bit offset). Both take only one clock cycle. Possible sources of confusion: Consider the following code, ram0 equ0x0000 *2 ;RAM word zero ram1 equ0x0001 *2 ;RAM word one ram2...
Page 114: Symbols And Explanation
Instruction Classification 4.4 Instruction Classification The machine level instruction set is divided into a number of classes. The classes are primarily divided according to field references associated with memory, hardware registers, and control fields. The following descriptions give class-encode bit assignments, the OP code value within the class, and the abbreviated field descriptions.
Page 115 Instruction Classification Table 4–11. Symbols and Explanation (Continued) Symbol Explanation next A Accumulator control bits as described in Table 4–6. [ next A ] The preincrement (++A) or predecrement (– –A) operation on accumulator pointers A n or A n ~. NOT condition on conditional jumps, conditional calls or test flag instructions.
Page 116 Instruction Classification Table 4–11. Instruction Classification (Continued) Class Sub- Description Class Register and memory reference Memory references that use R x ; all addressing modes available Memory references with short constant fields operating on R x Memory references with long constant fields operating on R x and others Memory references with long constant fields operating on R x and others General mMemory reference instructions I/O port and memory reference instructions...
Page 117: Classes And Opcode Definition
Instruction Classification Table 4–12. Classes and Opcode Definition Class 1a next A Class 1b Class 2a imm8 Class 2b next A A~ † Class 3 next A Class 4a Class 4b Class 4c Class 4d Class 5 Class 6a port4 Class 6b port6 Class 7a...
Page 118: Class 1 Instruction Encoding
Instruction Classification Class 1a provides the four basic instructions of load, store, add, and subtract between accumulator and data memory. Either the accumulator or the offset accumulator (A~ bit dependent) can be stored in memory with the MOV instruction. The MOV instruction can load the accumulator (or its offset) depending on the ~A bit.
Page 119 Instruction Classification Table 4–15. Class 1b Instruction Description Mnemonic Description OR A n , { adrs } Logical OR the contents of the data memory location in { adrs } ORS A n , { adrs } and the selected accumulator. Result(s) stored in accumulator(s).
Page 120: Class 2 Instructions: Accumulator And Constant Reference
Instruction Classification Table 4–15. Class 1b Instruction Description (Continued) Mnemonic Description MULAPL A n , { adrs } Multiply the MR register by the addressing mode { adrs } and add MULAPLS A n , { adrs } the lower 16 bits of the product to the accumulator. Latch the upper 16 bits into the PH register.
Page 121 Instruction Classification constants. Long constants (16 bits) and long string constants differ in that ref- erences are made to constants in the second word of the two-word instruction word. References made to a single 16 bit integer constant are immediate. That is, the actual constant value follows the first word opcode in memory.
Page 122: Class 3 Instruction: Accumulator Reference
Instruction Classification Table 4–18. Class 2b Instruction Description Mnemonic Description 0 ADD A n [~], A n [~], imm16 [, next A] Add long constant to accumulator (or offset accumulator if ADDS A n [~], A n [~], pma16 A~=1) and store result to accumulator (~A=0) or offset accumulator (~A=1).
Page 123 Instruction Classification between the accumulator and the MR, SV, or PH register. As with all accumula- tor referenced instructions, string operations are possible as well as premodi- fication of one of 4 indirectly referenced accumulator pointer registers (AP). Table 4–19. Class 3 Instruction Encoding next A Class 3 Table 4–20.
Page 124 Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) Mnemonic Description 0 1 0 0 0 XOR A n [~], A n ~, A n [, next A ] Logically exclusive accumulator with offset XORS A n [~], A n ~, A n accumulator and store the results in accumulator (~A=0 or 1).
Page 125 Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) Mnemonic Description 1 0 1 0 0 MOV SV, A n [~] [, next A ] Transfer accumulator(A~=0) or offset accumulator (A~=1) MOVS SV, A n [~] to SV register. Transfer status is modified. 1 0 1 0 1 MOV PH, A n [~] [, next A ] Transfer accumulator (A~=0) or offset accumulator (A~=1) MOVS PH, A n [~]...
Page 126: Class 4 Instructions: Address Register And Memory Reference
Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) Mnemonic Description 1 1 1 1 0 MUL A n [~] [, next A ] Multiply MR register by accumulator (A~=1) or offset MULS A n [~] accumulator (A~=0) and latch the rounded upper 16 bits of the resulting product into the PH register.
Page 127: Class 4D Instruction Description
Instruction Classification Table 4–22. Class 4a Instruction Description Mnemonic Description MOV { adrs }, R x Store R x register to data memory referred by addressing mode {adrs}. Modify transfer status. MOV R x , { adrs } Load R x with the value in data memory referred by addressing mode {adrs}. Modify transfer status.
Page 128: Class 5 Instruction Encoding
Instruction Classification 4.4.5 Class 5 Instructions: Memory Reference Class 5 instructions provide transfer to and from data memory and all registers except accumulators and R x which are included in classes 1 and 4. The registers referenced for both read and write operations are the multiplier register (MR), the product high register (PH), the shift value register (SV), the status register (STAT), the top of stack (TOS), the string register (STR), and the four accumulator pointer registers AP0 to AP3.
Page 129 Instruction Classification Table 4–27. Class 5 Instruction Description (Continued) Mnemonic Description 0 1 0 1 MOV { adrs }, TOS Store the contents of the top of stack (TOS) register to the data memory location referred by addressing mode { adrs }. Transfer status is modified. 0 1 1 0 STAG { adrs } Store 1 to the 17...
Page 130: Class 6A Instruction Encoding
Instruction Classification Table 4–27. Class 5 Instruction Description (Continued) Mnemonic Description 1 1 1 1 RPT { adrs } Load repeat counter with lower 8 bits of data memory location referred by addressing mode { adrs }. Interrupts are queued during execution. 1 1 1 1 MOV STAT, { adrs } Load status (STAT) register with effective data memory location referred...
Page 131: Class 6B Instruction Description
Instruction Classification Table 4–30. Class 6b Instruction Description Mnemonic Description IN A n [~], port6 Transfer the port’s 16 bit value to an accumulator. Port addresses 0–63 INS A n [~], port6 are valid. ALU status is modified. OUT port6 , A n [~] Transfer a 16 bit accumulator value to the addressed port.
Page 132: Class 7 Instruction Encoding And Description
Instruction Classification Table 4–31. Class 7 Instruction Encoding and Description VCALL vector8 vector8 J cc JMP *A n C cc CALL *An cc names Description cc name Not cc name Conditional on ZF=1 Conditional on SF=1 Conditional on CF=1 Conditional on ZF=0 and CF=0 Conditional on ZF=0 and CF=1 Conditional on SF=0 and ZF=0 Conditional if ZF=1 and OF=0...
Page 133: Class 8A Instruction Encoding
Instruction Classification Table 4–31. Class 7 Instruction Encoding and Description (Continued) cc names Description cc name Not cc name Unconditional Not assigned Not assigned Conditional on XSF Conditional on XZF Conditional on ! XSF and ! XZF Not assigned Not assigned Not assigned Not assigned Not assigned...
Page 134: Class 8A Instruction Description
Instruction Classification Table 4–33. Class 8a Instruction Description Mnemonic Description MOV TF n , { flagadrs } Load flag bit (17 bit) from data memory referred by flag addressing mode { flagadrs } to either TF1 or TF2 in status register. Load with inverted value if Not =1.
Page 135: Class 9A Instruction Encoding
Instruction Classification Table 4–35. Class 9a Instruction Encoding Class 9a Class 9b imm8 Class 9c AP n imm5 Class 9d ENDLOOP n Table 4–36. Class 9a Instruction Description Mnemonic Description FIRK A n , *R x Finite impulse response tap execution. When used with repeat counter will execute a 16 bit 16 bit multiplication between an indirect-addressed data memory buffer and program memory (coefficients).
Page 136: Class 9C Instruction Description
Bit, Byte, Word and String Addressing Table 4–38. Class 9c Instruction Description Mnemonic Description MOV AP n , imm6 Load the accumulator pointer (AP) with a five bit constant. ADD AP n , imm5 Add a five bit constant imm5 to the referenced accumulator pointer(AP). Table 4–39.
Page 137: Data Memory Organization And Addressing
Bit, Byte, Word and String Addressing is a string of bytes. The length of the byte string is stored in the string register (STR). To define the length of a string, the STR register should hold the length of the string minus 2. For example, if the length of a byte string is 10, then STR should be 8.
Page 138: Data Memory Address And Data Relationship
Bit, Byte, Word and String Addressing Flag address: The flag (or TAG) address uses linear addressing from 0 to the size of data memory in 17 bit wide words (0 to 639 for MSP50P614/ MSP50C614). Only the 17 bit is accessible. When a word memory location is read, the corresponding flag for that location is always loaded into the TAG bit of the status register (STAT).
Page 139: Data Memory Example
Bit, Byte, Word and String Addressing Figure 4–4. Data Memory Example Absolute Word Data Memory Location (even) = 2 * Data Memory MS Byte LS Byte (Absolute word memory location) Location (odd) Memory Location 0x0000 0x0000 0x12 0x34 0x0001 0x0001 0x0002 0x56 0x78...
Page 140 Bit, Byte, Word and String Addressing Example 4.5.7 MOV STR, 4–2 MOV AP0, 2 MOV R0, 0x0001 * 2 MOVBS A0, *R0++ Refer to Figure 4–4 for this example. The word-string length is 4. AP0 points to AC2 accumulator. R0 is loaded with 0x0002. The fourth instruction loads the value of the word-string at the RAM address in R0, 0x0002.
Page 141: Msp50P614/Msp50C614 Computational Modes
MSP50P614/MSP50C614 Computational Modes Example 4.5.10 MOV STR, 0 SFLAG *0x00032 MOVS A0, *0x0031 * 2 RFLAG *0x00032 MOVS A0, *0x0031 * 2 Refer to Figure 4–4 for this example. This example is to illustrate the effect of the tag/flag bit when used with a string instruction. The string register (STR) is loaded with 0 (string length of 2).
Page 142: Msp50P614/Msp50C614 Computational Modes
MSP50P614/MSP50C614 Computational Modes Table 4–41. MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Function Instruction Mode Instruction Sign extension STAT.XM = 1 produces sign extension on data as it is passed into accumulators. This mode copies the 16 bit of the data in the multiplier/multiplicand to the 17 bit.
Page 143 MSP50P614/MSP50C614 Computational Modes Example 4.6.2 MOV STR, 2–2 ; string length=2 MOV MR, 0x8000 MOV A0, 0x8000, ++A ; load MS Byte MOV A0, 0x0000, ––A ; load LS Byte MULTPLS A0, A0 This example illustrates the sign extension mode on a string during multiplication.
Page 144 MSP50P614/MSP50C614 Computational Modes Example 4.6.1 SOVM MOV A0, 0x7FFE ADD A0, 5 In this example, we set the overflow mode (OM = 1 of STAT). Adding 0x7FFE with 5 causes an overflow (OF = 1 of STAT). Since the expected result is a positive value, the accumulator saturates to the largest representable value, 0x7FFF.
Page 145: Hardware Loop Instructions
Hardware Loop Instructions high word of the result is stored in the PH register and is 0x3FFF. The low word is stored in A0~ as 0x0001. If the two numbers are considered as Q15 fraction- al numbers (all bits are to the right of the decimal point), then the result will be a Q30 number.
Page 146: Hardware Loops In Msp50P614/Msp50C614
Hardware Loop Instructions the execution of a string instruction, interrupts are queued. Queued interrupts are serviced according to their priority after the string operation is complete. In addition to repeat and string instructions, the combination of repeated string instructions has a very useful function. Since there is only one counter to control the hardware repeat count, it is not possible to nest repeats and strings.
Page 147: Initial Processor State For String Instructions
String Instructions 4.8 String Instructions Class 1, 2, 3, and 6 instructions can have string modes. During the execution of string instruction, STR register value plus 2 is assumed as string length. An accumulator string is a group of consecutive accumulators spanning from A n to the next N consecutive accumulators (N is the length of the string).
Page 148 String Instructions A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR = 3–2=1, defines a string length of 3. Final result, A1~ string = 0x233EFBCA1223 + 0x9086EE3412AC = 0xB3C5E9FE24CF, AC5=0x24CF, AC6=0xE9FE, AC7=0xB3C5, STR=2 (unchanged). Notice that this instruction has accumulated a carry. Special String Sequences: There are two string instructions that have a special meaning.
Page 149: Lookup Instructions
Lookup Instructions 4.9 Lookup Instructions Table lookup instructions transfer data from program memory (ROM) to data memory or accumulators. These instructions are useful for reading permanent ROM data into the user program for manipulation. For example, lookup tables can store initial filter coefficients, characters for an LCD display which can be read for display in the LCD screen, etc.
Page 150 Lookup Instructions Lookup instructions make use of the data pointer (DP) internally. The DP stores the address of the program memory location, loads the value to the destination, and increments it automatically after every load. Thus, the value of the DP is always the last used program memory address plus one. The content of DP changes after the execution of lookup instructions.
Page 151: Fir Filter Structure
Input/Output Instructions 4.10 Input/Output Instructions The MSP50P614/MSP50C614 processor communicates with other on-chip logic as well as external hardware through a parallel I/O interface. Up to 40 I/O ports are addressable with instructions that provide bidirectional data transfer between the I/O ports and the accumulators. Data input is performed with the IN instruction (Class 6).
Page 152 Special Filter Instructions N tap filters ideally require 2N multiply–accumulates. Four instructions are provided to compute this equation: FIR, FIRK, COR and CORK. All filter instructions require overflow modes to be reset since these instructions have built in overflow hardware. In addition, these instructions must be used with a RPT instruction.
Page 153 Special Filter Instructions theory requires). The second to last RAM location in the circular buffer is tagged using an STAG instruction. Below is an example of how to set up circu- lar buffering with FIR or COR. When using the FIR or COR instruction with circular buffering, RAM needs to be allocated for the circular buffer and the filter coefficients.
Page 154 Special Filter Instructions After the FIR or COR instruction executes, the new startOfBuff will be the last location in the circular buffer. After another FIR/COR instruction, the new startOfBuff will be the second to last location in the circular buffer, and so The second detail is the STAT register.
Page 155 Special Filter Instructions A0,*nextSample ;Replace last sample with newest sample *R0,A0 ; and update the start of the *startOfBuff,R0 ; circular buffer to here (R0) First, the overflow mode must be reset. Next, R5 must be loaded with the wrap around value of the circular buffer.
Page 156 Special Filter Instructions Any combination of registers different from the above will yield incorrect results with the FIR/COR instruction. 0x0106 0x010 x[k–3] x[k–2] Use R5 to wrap around x[k] x[k–1] 0x0100 0x0102 After FIR/COR execution The STAT register is saved in the filterSTAT_tag location. The output of the fil- tering operation in the example is located in AC0 (lower word) and AC1 (high word).
Page 157 Special Filter Instructions Important note about setting the STAT register It is very important to consider the initial value of the filterSTAT_tag variable. Failure to set up the filterSTAT_tag variable can cause incorrect results in FIR/ COR operations. Overflow mode must always be reset. The overflow bit of the STAT register may not be set.
Page 158 Special Filter Instructions STAT,*filterSTAT_tag ;load STAT with last filter tag status N–2 firk A0,*R0++ ;Do one sample ––> 32 bit result *filterSTAT_tag,STAT ;save STAT with last filter tag status ;R0 now points to the last sample movs *ySampleOut,A0 ;FIR outputs bits 0–15 in AC0, 16–32 in AC1 A0,*nextSample ;Replace last sample with...
Page 159: Setup And Execution Of Msp50P614/Msp50C614 Filter Instructions, N+1 Taps
Special Filter Instructions Figure 4–6. Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 Taps FIRK/CORK only Program memory (FIRK/CORK) coeff_array address Î Î Î Î Î Î even coeff_array address Î Î Î Î Î Î {R1,R3,R5,R7} Î Î Î Î Î Î even coeff_array sample_buf address...
Page 160: Filter Instruction And Circular Buffering For N+1 Tap Filter
Special Filter Instructions Figure 4–7. Filter Instruction and Circular Buffering for N+1 Tap Filter even CORK/FIRK only coeff_array if TAG = 1 R5 = –2(N+1) coeff_array COR/FIR only even even 16 Bits 16 Bits coeff_array x [k] h[0] h[1] x [k–1] x [k–2] h[2] h[3]...
Page 161: Conditionals
Conditionals 4.12 Conditionals The condition bits in the status register (STAT) are used to modify program control through conditional branches and calls. Various combinations of bits are available to provide a rich set of conditional operations. These condition bits can also be used in Boolean operations to set the test flags TF1 and TF2 in the status register.
Page 162: Legend
Legend 4.13 Legend All instructions of the MSP50P614/MSP50C614 use the following syntax: name [ dest ] [ , src ] [ , src1 ] [ , mod ] name Name of the instruction. Instruction names are shown in bold letter through out the text. dest Destination of the data to be stored after the execution of the instruction.
Page 163 Legend Symbol Meaning Select offset accumulator as the source if this bit is 1. Used in opcode encoding only. Select offset accumulator as the destination accumulator if this bit is 1. Used in opcode encod- ing only. Select offset accumulator as the source if this bit is 0. Used in opcode encoding only. Can be either ~A or A~ based on opcode (or instruction).
Page 164 Legend Symbol Meaning Value in repeat counter loaded by RPT instructions Value in string register STR Overflow flag offset [ n ] n bit offset from a reference register. Overflow mode Program counter, 16 bits pma [ n ] n bit program memory address. For example, pma8 means 8-bit program memory address. If n is not specified, defaults to pma16 .
Page 165: Auto Increment And Decrement
Legend Table 4–45. Auto Increment and Decrement Operation next A No modification Auto increment Auto Decrement – –A Table 4–46. Addressing Mode Bits and adrs Field Description Addressing Mode Encoding String† String† Relative Repeat { adrs } Clocks Words Addressing Addressing Operation Operation...
Page 166: Individual Instruction Descriptions
Individual Instruction Descriptions 4.14 Individual Instruction Descriptions In this section, individual instructions are discussed in detail. Use the conditionals in Section 4.12 and the legend in Section 4.13 to help with individual instruction descriptions. Each instruction is discussed in detail and provides the following information: Assembler syntax Clock cycles required with or without repeat instructions...
Page 167 Individual Instruction Descriptions 4.14.1 ADD Add word Syntax [ label ] dest , src [, src1 ] [, mod ] Clock, clk Words, w With RPT, clk name Class A n [~], A n , { adrs } [, next A ] Table 4–46 Table 4–46 Table 4–46...
Page 168 Individual Instruction Descriptions Description Syntax Description ADD dest , src ADD src with dest and store the result to dest . ADD dest , src , src1 [, mod ] ADD src1 with src and store the result to dest . Premodify the mod before execution.
Page 169 Individual Instruction Descriptions 4.14.2 ADDB ADD BYTE Syntax [ label ] name dest, src Clock, clk Words, w With RPT, clk Class ADDB A n , imm8 ADDB R x , imm8 dest dest + src Execution PC + 1 dest is A n : Flags Affected OF, SF, ZF, CF are set accordingly...
Page 170 Individual Instruction Descriptions 4.14.3 ADDS Add String Syntax [ label ] name dest, src, src1 Clock, clk Words, w With RPT, clk Class A n [~], A n , { adrs } ADDS Table 4–46 Table 4–46 Table 4–46 ADDS A n [~], A n [~], pma16 ADDS A n [~], A n ~, A n...
Page 171 Individual Instruction Descriptions Example 4.14.3.3 ADDS A1, A1~, A1 Add accumulator string A1 to accumulator string A1~, put result in accumulator string A1. Example 4.14.3.4 MULAPL A0, A0~ ADDS A0, A0~, PH The first instruction multiplies MR and A0~, adds PL to A0, and stores the result in A0. The second instruction adds PH to the second word of memory string A0 and puts the result in accumulator string A0.
Page 172 Individual Instruction Descriptions 4.14.4 AND Bitwise AND Syntax [label] name dest, src [ , src1 ] [ , mod ] Clock, clk Word, w With RPT, clk Class A n , { adrs } Table 4–46 Table 4–46 A n [~], A n [~], imm16 [, next A ] A n [~], A n ~, A n [, next A ] TF n , [!]{ flagadrs } TF n , { cc } [, R x ]...
Page 173 Individual Instruction Descriptions See Also ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS Example 4.14.4.1 AND A3, *R4— – And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after the AND operation.
Page 174 Individual Instruction Descriptions 4.14.5 ANDB Bitwise AND Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ANDB A n , imm8 Execution dest dest AND src byte PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions ANDB A n , imm8...
Page 175 Individual Instruction Descriptions 4.14.6 ANDS Bitwise AND String Syntax [label] name dest, src [ , src1 ] Clock, clk Word, w With RPT, clk Class ANDS A n , { adrs } Table 4–46 Table 4–46 ANDS A n [~], A n [~], pma16 ANDS A n [~], A n ~, A n dest string...
Page 176 Individual Instruction Descriptions 4.14.7 BEGLOOP Begin Loop Syntax [label] name Clock, clk Word, w With RPT, clk Class † BEGLOOP † Loop must end with ENDLOOP. Execution Save next instruction address (PC + 1) ( mask interrupts ) PC + 1 Flags Affected none Opcode...
Page 177 Individual Instruction Descriptions 4.14.8 CALL Unconditional Subroutine Call Syntax [label] name address Clock, clk Word, w With RPT, clk Class CALL pma16 CALL *A n Execution PC + 2 pma16 or *An R7 + 2 Flags Affected None Opcode Instructions CALL pma16 pma16 CALL *A n...
Page 178 Individual Instruction Descriptions 4.14.9 C cc Conditional Subroutine Call Syntax [label] name address Clock, clk Word, w With RPT, clk Class † C cc pma16 † Cannot immediately follow a CALL instruction with a return instruction. If true If Not true [ label ] pma16 [ label ]...
Page 179: Names For Cc
Individual Instruction Descriptions Table 4–48. Names for cc cc names Description True condition ( Not true condition) cc name Not cc name 0 0 0 0 0 Conditional on ZF=1 ( Not condition ZF=0) 0 0 0 0 1 Conditional on SF=1 ( Not condition SF=0) 0 0 0 1 0 Conditional on CF=1 ( Not condition CF=0) Conditional on ZF=0 and CF=0 ( Not condition ZF 0 or CF 0)
Page 180 Individual Instruction Descriptions Description If cc condition in Table 4–48 is true, PC + 2 is pushed onto the stack and the second word operand is loaded into the PC. If the condition is false, execution defaults to a NOP. A C cc instruction cannot be followed by a return (RET) instruction.
Page 181 Individual Instruction Descriptions Syntax Alternate Syntax Description CRC pma16 Conditional call on RCF = 1 CRNC pma16 Conditional call on RCF = 0 † CRE pma16 CRZ pma16 Conditional call on RZF = 1 (equal) † CRNE pma16 CRNZ pma16 Conditional call on RZF = 0 (not equal) †...
Page 182 Individual Instruction Descriptions 4.14.10 CMP Compare Two Words [label] name src, src1 [ , mod ] Clock, clk Word, w With RPT, clk Class A n , { adrs } Table 4–46 Table 4–46 A n [~], imm16 [, next A ] A n , A n ~ [, next A ] A n ~, A n [, next A ] †...
Page 183 Individual Instruction Descriptions Example 4.14.10.3 CMP R2, 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly. Example 4.14.10.4 CMP R0, R5 Compare value at R0 to R5 and change the STAT flags accordingly. Assembly Language Instructions 4-91...
Page 184 Individual Instruction Descriptions 4.14.11 CMPB Compare Two Bytes Syntax [label] name src, src1 Clock, clk Word, w With RPT, clk Class CMPB A n , imm8 CMPB R x , imm8 Execution status flags set by src – src1 byte PC + 1 Flags Affected src is A n :...
Page 185 Individual Instruction Descriptions 4.14.12 CMPS Compare Two Strings Syntax [ label ] name src, src1 Clock, clk Word, w With RPT, clk Class CMPS A n , { adrs } Table 4–46 Table 4–46 CMPS A n [~], pma16 A n , A n ~ CMPS CMPS A n ~, A n...
Page 186 Individual Instruction Descriptions 4.14.13 COR Correlation Filter Function Syntax [ label ] name dest, src Clock, clk Word, w With RPT, clk Class A n , *R x Execution With RPT N–2: ( mask interrupts ) RPT counter = N–2 MR = h [0] = first filter coefficient x = sample data pointed by R x even...
Page 187 Individual Instruction Descriptions 4.14.14 CORK Correlation Filter Function Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class CORK A n , *R x Execution With RPT N–2: ( mask interrupts ) RPT counter = N–2 MR = h [0] = first filter coefficient x = sample data pointed at by R x even h [1] = second filter coefficient pointed by DP...
Page 188 Individual Instruction Descriptions 4.14.15 ENDLOOP End Loop Syntax [label] name Clock, clk Word, w With RPT, clk Class [ n ] ENDLOOP Execution If (R4 decrement R4 by n (1 or 2) first address after BEGLOOP else PC + 1 Flags Affected None Opcode...
Page 189 Individual Instruction Descriptions 4.14.16 EXTSGN Sign Extend Word Syntax [label] name dest [ , mod ] Clock, clk Word, w With RPT, clk Class A n [~] [, next A ] EXTSGN [premodify AP if mod specified] Execution new most significant word of dest STAT.SF PC + 1 Flags Affected...
Page 190 Individual Instruction Descriptions 4.14.17 EXTSGNS Sign Extend String Syntax [label] name dest Clock, clk Word, w With RPT, clk Class A n [~] EXTSGNS new most significant word of dest Execution STAT.SF PC + 1 Flags Affected None Opcode Instructions EXTSGNS A n [~] Description Extend the sign bit (SF) of most significant word an additional 16 bits to the left.
Page 191 Individual Instruction Descriptions MOV AP1, 3 ; Point to loc corresponding to ; extended word in acc MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY EXTSGN A1 ; not string version as above Alternatively, the following code can do the same thing but requires more code: MOV AP0, 0 ;...
Page 192 Individual Instruction Descriptions 4.14.18 FIR FIR Filter Function (Coefficients in RAM) Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class A n , *R x Execution With RPT N–2: ( mask interrupts ) RPT counter = N–2 MR = h [0] = first filter coefficient x = sample data pointed at by R x even...
Page 193 Individual Instruction Descriptions See Also RPT, FIRK, COR, CORK Example 4.14.18.1 RPT 0 FIR A0, *R0 Computes the calculation for 2 tap FIR filter with 32-bit accumulation. See section 4.11 for more detail on the setup of coefficients and sample data. Assembly Language Instructions 4-101...
Page 194 Individual Instruction Descriptions 4.14.19 FIRK FIR Filter Function (Coefficients in ROM) Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class A n , *R x FIRK Execution With RPT N–2: ( mask interrupts ) RPT counter = N–2 MR = h [0] = first filter coefficient x = sample data pointed by R x even...
Page 195 Individual Instruction Descriptions 4.14.20 IDLE Halt Processor Syntax [label] name Clock, clk Word, w With RPT, clk Class IDLE Execution Stop processor clocks PC + 1 Flags Affected None Opcode Instructions IDLE Description Halts execution of processor. An external interrupt wakes the processor. This instruction is the only instruction to enter one of the three low power modes defined in section 2.11.
Page 196 Individual Instruction Descriptions 4.14.21 IN Input From Port Into Word Syntax [label] name dest, src1 Clock, clk Word, w With RPT, clk Class { adrs }, port4 Table 4–46 Table 4–46 A n [~], port6 Execution dest content of port6 or port4 PC + w Flags Affected dest is A n :...
Page 197 Individual Instruction Descriptions 4.14.22 INS Input From Port Into String Syntax [label] name src, src1 Clock, clk Word, w With RPT, clk Class A n [~], port6 Execution dest content of port6 PC + 1 Flags Affected dest is A n: OF, SF, ZF, CF are set accordingly Opcode Instructions...
Page 198 Individual Instruction Descriptions 4.14.23 INTD Interrupt Disable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTD Execution STAT.IM (IM is STAT bit 4) PC + 1 Flags Affected None Opcode Instructions INTD Description Disables interrupts. Resets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 0.
Page 199 Individual Instruction Descriptions 4.14.24 INTE Interrupt Enable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTE Execution STAT.IM (IM is STAT bit 4) PC + 1 Flags Affected None Opcode Instructions INTE Description Enables interrupts. Sets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 1.
Page 200 Individual Instruction Descriptions 4.14.25 IRET Return From Interrupt Syntax [label] name Clock, clk Word, w With RPT, clk Class IRET Execution R7 – 2 Flags Affected None Opcode Instructions IRET See Also RET, CALL, C cc , INTE, INTD Description Return from interrupt.
Page 201 Individual Instruction Descriptions 4.14.26 J cc Conditional Jumps Syntax [label] name pma16 [, Rmod ] Clock, clk Word, w With RPT, clk Class J cc pma16 [, Rmod ] If true If Not true [label] pma16 [ , Rmod ] [label] pma16 [ , Rmod ] [label]...
Page 202 Individual Instruction Descriptions Opcode Instructions J cc pma16 pma16 J cc pma16 R x ++ pma16 J cc pma16 R x –– pma16 J cc pma16 , R x ++R5 pma16 cc names Description Description True condition ( Not true condition) cc name Not cc name Conditional on ZF=1 ( Not condition ZF=0)
Page 203 Individual Instruction Descriptions cc names Description Description True condition ( Not true condition) cc name Not cc name reserved reserved reserved reserved Description PC is replaced with second word operand if condition is true (or unconditional). If test condition is false, a NOP is executed. Syntax Alternate Description...
Page 204 Individual Instruction Descriptions Syntax Alternate Description Instruction JRNLZP pma16 [, Rmod ] Conditional jump on R x 0 after post-mod JRZP pma16 [, Rmod ] Conditional jump on R x = 0 after post-mod JRNZP pma16 [, Rmod ] Conditional jump on R x 0 after post-mod JS pma16 [, Rmod ] Conditional jump on SF = 1...
Page 205 Individual Instruction Descriptions 4.14.27 JMP Unconditional Jump Syntax [label] name dest [, mod ] Clock, clk Word, w With RPT, clk Class pma16 pma16 , R x ++ pma16, R x – – pma16, R x ++R5 *A n dest Execution [Post–modify R x if specified] Flags Affected...
Page 206 Individual Instruction Descriptions 4.14.28 MOV Move Data Word From Source to Destination Syntax [label] name dest, src, [, next A ] Clock, clk Word, w With RPT, clk Class { adrs }, A n [~] [, next A ] Table 4–46 Table 4–46 A n [~], { adrs } [, next A ] Table 4–46...
Page 207 Individual Instruction Descriptions [label] name dest, src, [, next A ] Clock, clk Word, w With RPT, clk Class TF n , { cc } [, R x ] STR, imm8 SV, imm4 AP n , imm5 Execution [premodify AP if mod specified] dest PC + w Flags Affected...
Page 208 Individual Instruction Descriptions Instructions MOV R x , R5 MOV SV, imm4 imm4 MOV SV, { adrs } 4 adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MOV PH, { adrs } adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MOV MR, { adrs } adrs dma16 (for direct) or offset16 (long relative) [see section 4.13]...
Page 209 Individual Instruction Descriptions Description Copy value of src to dest . Premodification of accumulator pointers is allowed with some operand types. Syntax Description † MOV A n [~], { adrs } [, next A ] Move data memory word to A n [~] MOV { adrs }, A n [~] [, next A ] Move A n [~] word to data memory †...
Page 210 Individual Instruction Descriptions Syntax Description MOV STR, imm8 Move immediate byte to String Register (STR) MOV AP n , imm5 Move immediate 5-bit value to AP n register † Accumulator condition flags are modified to reflect the value loaded into either A n or A n ~. ‡...
Page 211 Individual Instruction Descriptions Example 4.14.28.13 MOV R1, 0x0200 * 2 Load immediate word memory address 0x0200 to R1. Example 4.14.28.14 MOV R7, (0x0280 – 32) * 2 Load R7 (stack register) with the starting value of stack, i.e., 0x0260. Example 4.14.28.15 MOV *0x0200 * 2, R0 Store R0 to data memory word location 0x0200.
Page 212 Individual Instruction Descriptions 4.14.29 MOVAPH Move With Adding PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVAPH A n , MR, { adrs } Table 4–46 Table 4–46 Execution A n + PH contents of { adrs } PC + w Flags Affected...
Page 213 Individual Instruction Descriptions 4.14.30 MOVAPHS Move With Adding PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVAPHS A n , MR, { adrs } Table 4–46 Table 4–46 Execution A n + PH contents of { adrs } PC + w Flags Affected...
Page 214 Individual Instruction Descriptions 4.14.31 MOVB Move Byte From Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVB A n , { adrs } Table 4–46 Table 4–46 MOVB { adrs }, A n Table 4–46 Table 4–46 MOVB A n , imm8...
Page 215 Individual Instruction Descriptions Example 4.14.29.2 MOVB *R2, A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2. Example 4.14.29.3 MOVB A0, 0xf2 Load accumulator A0 with value of 0xf2. Example 4.14.29.4 MOVB MR, 34 Load MR register with immidiate value of 34 (decimal).
Page 216 Individual Instruction Descriptions 4.14.32 MOVBS Move Byte String from Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVBS A n , { adrs } Table 4–46 Table 4–46 MOVBS { adrs }, A n Table 4–46 Table 4–46 Execution...
Page 217 Individual Instruction Descriptions 4.14.33 MOVS Move String from Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVS A n [~], { adrs } Table 4–46 Table 4–46 MOVS { adrs }, A n [~] Table 4–46 Table 4–46 MOVS...
Page 218 Individual Instruction Descriptions Description Copy value of src string to dest string. Premodification of accumulator pointers is allowed with some operand types. Syntax Description MOVS A n [~], { adrs } Move data memory word string to A n [~] string MOVS { adrs }, A n [~] Move A n [~] string to data memory MOVS { adrs }, *A n...
Page 219 Individual Instruction Descriptions 4.14.34 MOVSPH Move With Subtract from PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVSPH A n , MR, { adrs } Table 4–46 Table 4–46 Execution A n – PH contents of { adrs } PC + w Flags Affected...
Page 220 Individual Instruction Descriptions 4.14.35 MOVSPHS Move String With Subtract From PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVSPHS A n , MR, { adrs } Table 4–46 Table 4–46 Execution A n (second word) – PH contents of { adrs} PC + w Flags Affected...
Page 221 Individual Instruction Descriptions 4.14.36 MOVT Move Tag From Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVT { adrs }, TF n Table 4–46 Table 4–46 Execution dest PC + w Flags Affected None Opcode Instructions...
Page 222 Individual Instruction Descriptions 4.14.37 MOVU Move Data Unsigned Syntax [label] name dest, src [, mod ] Clock, clk Word, w With RPT, clk Class MOVU MR, A n [~] [, next A ] MOVU MR, { adrs } Table 4–46 Table 4–46 Execution [premodify AP if mod specified]...
Page 223: Valid Moves/Transfer In Msp50P614/Msp50C614 Instruction Set
Individual Instruction Descriptions Figure 4–8. Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set MR/SV xxxxxx xxxx00 Immediate Flag Bit STAT NOTE: B = Byte move possible. S = String move possible. R5 can be moved to Rx, An[–] to An[–] Assembly Language Instructions 4-131...
Page 224 Individual Instruction Descriptions 4.14.38 MUL Multiply (Rounded) Syntax [label] name src [, mod ] Clock, clk Word, w With RPT, clk Class A n [~] [, next A ] { adrs } Table 4–46 Table 4–46 Execution [premodify AP if mod specified] PH,PL MR * src PC + w...
Page 225 Individual Instruction Descriptions 4.14.39 MULS Multiply String With No Data Transfer Syntax [label] name Clock, clk Word, w With RPT, clk Class MULS A n [~] Execution PH,PL MR * src string PC + 1 Flags Affected None Opcode Instructions MULS A n [~] Multiply MR and the value in src .
Page 226 Individual Instruction Descriptions 4.14.40 MULAPL Multiply and Accumulate Result Syntax [label] name dest, src [ , mod ] Clock, clk Word, w With RPT, clk Class MULAPL A n , { adrs } Table 4–46 Table 4–46 MULAPL A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified] PH,PL...
Page 227 Individual Instruction Descriptions 4.14.41 MULAPLS Multiply String and Accumulate Result Syntax [label] name dest, src [ , mod ] Clock, clk Word, w With RPT, clk Class MULAPLS A n , { adrs } Table 4–46 Table 4–46 MULAPLS A n [~], A n [~] Execution PH,PL MR * src...
Page 228 Individual Instruction Descriptions 4.14.42 MULSPL Multiply and Subtract PL From Accumulator Syntax [label] name dest, src [ , mod ] Clock, clk Word, w With RPT, clk Class MULSPL A n , { adrs } Table 4–46 Table 4–46 MULSPL A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified]...
Page 229 Individual Instruction Descriptions 4.14.43 MULSPLS Multiply String and Subtract PL From Accumulator Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MULSPLS A n , { adrs } Table 4–46 Table 4–46 MULSPLS A n [~], A n [~] Execution PH,PL MR * src...
Page 230 Individual Instruction Descriptions 4.14.44 MULTPL Multiply and Transfer PL to Accumulator Syntax [label] name dest, src [ , mod ] Clock, clk Word, w With RPT, clk Class MULTPL A n , { adrs } Table 4–46 Table 4–46 MULTPL A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified]...
Page 231 Individual Instruction Descriptions 4.14.45 MULTPLS Multiply String and Transfer PL to Acumulator Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MULTPLS A n , { adrs } Table 4–46 Table 4–46 MULTPLS A n [~], A n [~] Execution PH, PL MR * src...
Page 232 Individual Instruction Descriptions 4.14.46 NEGAC Two’s Complement Negation of Accumulator Syntax [label] name dest, src [,mod] Clock, clk Word, w With RPT, clk Class NEGAC A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified] dest –...
Page 233 Individual Instruction Descriptions 4.14.47 NEGACS Two’s Complement Negation of Accumulator String Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class NEGACS A n [~], A n [~] Execution dest – src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions...
Page 234 Individual Instruction Descriptions 4.14.48 NOP No Operation Syntax [label] name Clock, clk Word, w With RPT, clk Class Execution PC + 1 (No operation) Flags Affected None Opcode Instructions Description This instruction performs no operation. It consumes 1 clock of execution time and 1 word of program memory.
Page 235 Individual Instruction Descriptions 4.14.49 NOTAC One’s Complement Negation of Accumulator Syntax [label] name dest, src [ , mod ] Clock, clk Word, w With RPT, clk Class NOTAC A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified] dest NOT src PC + 1...
Page 236 Individual Instruction Descriptions 4.14.50 NOTACS One’s Complement Negation of Accumulator String Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class NOTACS A n [~], A n [~] Execution dest NOT src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions...
Page 237 Individual Instruction Descriptions 4.14.51 OR Bitwise Logical OR Syntax [label] name dest, src [, src1] [, mod] Clock, clk Word, w With RPT, clk Class A n , { adrs } Table 4–46 Table 4–46 A n [~], A n [~], imm16 [, next A ] A n [~], A n ~, A n [, next A ] TF n , { flagadrs } TF n , { cc } [, R x ]...
Page 238 Individual Instruction Descriptions See Also ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NOTACS Example 4.14.51.1 OR A0, *R0++R5 OR accumulator A0 with the value in data memory address stored in R0 and store result in accumulator A0, Add R5 to R0 after execution. Example 4.14.51.2 OR A1, A1, 0xF0FF, ++A Preincrement pointer AP1.
Page 239 Individual Instruction Descriptions 4.14.52 ORB Bitwise OR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class A n , imm8 Execution dest dest OR src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions ORB A n , imm8...
Page 240 Individual Instruction Descriptions 4.14.53 ORS Bitwise OR String Syntax [label] name dest, src [, src1 ] Clock, clk Word, w With RPT, clk Class A n , { adrs } Table 4–46 Table 4–46 A n [~], A n [~], pma16 A n [~], A n ~, A n Execution dest...
Page 241 Individual Instruction Descriptions 4.14.54 OUT Output to Port Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class port4 , { adrs } Table 4–46 port6 , A n [~] Table 4–46 Execution port4 or port6 PC + w Flags Affected XSF, XZF are set accordingly src is { adrs }:...
Page 242 Individual Instruction Descriptions 4.14.55 OUTS Output String to Port Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class OUTS port6 , A n [~] Execution port6 PC + 1 Flags Affected XSF, XZF are set accordingly Opcode Instructions OUTS port6 , A n [~]...
Page 243 Individual Instruction Descriptions 4.14.56 RET Return From Subroutine (CALL, C cc ) Syntax [label] name Clock, clk Word, w With RPT, clk Class Execution R7 – 2 Flags Affected None Opcode Instructions Description Return from call or vectored call. Pop stack to program counter, continue execution.
Page 244 Individual Instruction Descriptions 4.14.57 RFLAG Reset Memory Flag Syntax [label] name Clock, clk Word, w With RPT, clk Class RFLAG { flagadrs } Execution memory flag bit at { flagadrs } data memory location PC + 1 Flags Affected None Opcode Instructions RFLAG {flagadrs}...
Page 245 Individual Instruction Descriptions 4.14.58 RFM Reset Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class Execution STAT.FM PC + 1 Flags Affected None Opcode Instructions Description Resets fractional mode. Clears bit 3 in status register (STAT). Disable multiplier shift mode for unsigned fractional or integer arithmetic.
Page 246 Individual Instruction Descriptions 4.14.59 ROVM Reset Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class ROVM Execution STAT.OM PC + 1 Flags Affected None Opcode Instructions Description Resets overflow mode in status register bit 2 (the OM bit). Disable ALU saturation output (normal mode).
Page 247 Individual Instruction Descriptions 4.14.60 RPT Repeat Next Instruction Syntax [label] name Clock, clk Word, w With RPT, clk Class { adrs } Table 4–46 imm8 Execution IF RPT { adrs } load src to repeat counter. ELSE load imm8 to repeat counter. ( mask interrupt ) repeat next instruction (repeat counter value + 2) times.
Page 248 Individual Instruction Descriptions 4.14.61 RTAG Reset Tag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class RTAG { adrs } Table 4–46 Table 4–46 Execution memory tag bit at { adrs } data memory location PC + 1 Flags Affected None Opcode...
Page 249 Individual Instruction Descriptions 4.14.62 RXM Reset Extended Sign Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class Execution STAT.XM PC + 1 Flags Affected None Opcode Instructions Description Reset extended sign mode status register bit 0 (the XM bit) to 0. See Also Example 4.14.62.1 Resets the sign extension mode to normal mode.
Page 250 Individual Instruction Descriptions 4.14.63 SFLAG Set Memory Flag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class SFLAG { flagadrs } Execution memory flag bit at { flagadrs } data memory location PC + 1 Flags Affected None Opcode Instructions...
Page 251 Individual Instruction Descriptions 4.14.64 SFM Set Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class Execution STAT.FM PC + 1 Flags Affected None Opcode Instructions Description Sets bit 3 (the FM bit) in status register (STAT) to 1. Enable multiplier shift mode for signed fractional arithmetic.
Page 252 Individual Instruction Descriptions 4.14.65 SHL Shift Left Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class A n [~] [, next A ] Execution [premodify AP if mod specified] PH, PL src << SV PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode...
Page 253 Individual Instruction Descriptions 4.14.66 SHLAC Shift Left Accumulator Syntax [label] name dest, src [, mod ] Clock, clk Word, w With RPT, clk Class SHLAC A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified] dest src <<...
Page 254 Individual Instruction Descriptions 4.14.67 SHLACS Shift Left Accumulator String Individually Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHLACS A n [~], A n [~] Execution dest src << 1 PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions...
Page 255 Individual Instruction Descriptions 4.14.68 SHLAPL Shift Left with Accumulate Syntax [label] name dest , src Clock, clk Word, w With RPT, clk Class [, mod ] SHLAPL A n , { adrs } Table 4–46 Table 4–46 SHLAPL A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified] PH, PL...
Page 256 Individual Instruction Descriptions 4.14.69 SHLAPLS Shift Left String With Accumulate Syntax [label] name dest , src Clock, clk Word, w With RPT, clk Class SHLAPLS A n , { adrs } Table 4–46 Table 4–46 SHLAPLS A n [~], A n [~] Execution PH, PL src <<...
Page 257 Individual Instruction Descriptions 4.14.70 SHLS Shift Left Accumulator String to Product Syntax [label] name dest Clock, clk Word, w With RPT, clk Class SHLS A n [~] Execution PH, PL src << SV PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions SHLS A n [~]...
Page 258 Individual Instruction Descriptions 4.14.71 SHLSPL Shift Left With Subtract PL Syntax [label] name dest , src Clock, clk Word, w With RPT, clk Class [, mod ] A n , { adrs } SHLSPL Table 4–46 Table 4–46 SHLSPL A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified] PH, PL...
Page 259 Individual Instruction Descriptions 4.14.72 SHLSPLS Shift Left String With Subtract PL Syntax [label] name dest , src Clock, clk Word, w With RPT, clk Class SHLSPLS A n , { adrs } Table 4–46 Table 4–46 SHLSPLS A n [~], A n [~] Execution PH, PL src <<...
Page 260 Individual Instruction Descriptions 4.14.73 SHLTPL Shift Left and Transfer PL to Accumulator Syntax [label] name dest , src Clock, clk Word, w With RPT, clk Class [, mod ] SHLTPL A n , { adrs } Table 4–46 Table 4–46 SHLTPL A n [~], A n [~] [, next A ] Execution...
Page 261 Individual Instruction Descriptions 4.14.74 SHLTPLS Shift Left String and Transfer PL to Accumulator Syntax [label] name dest , src Clock, clk Word, w With RPT, clk Class SHLTPLS A n , { adrs } Table 4–46 Table 4–46 SHLTPLS A n [~], A n [~] Execution PH, PL src <<...
Page 262 Individual Instruction Descriptions 4.14.75 SHRAC Shift Accumulator Right Syntax [label] name dest, src, [, mod ] Clock, clk Word, w With RPT, clk Class SHRAC A n [~], A n [~] [, next A ] Execution [premodify AP if mod specified] dest src >>...
Page 263 Individual Instruction Descriptions 4.14.76 SHRACS Shift Accumulator String Right Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHRACS A n [~], A n [~] Execution dest src >> 1 PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions SHRACS A n [~], A n [~]...
Page 264 Individual Instruction Descriptions 4.14.77 SOVM Set Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SOVM Execution STAT.OM PC + 1 Flags Affected None Opcode Instructions SOVM Description Sets overflow mode in status register (STAT) bit 2 to 1. Enable ALU saturation output (DSP mode).
Page 265 Individual Instruction Descriptions 4.14.78 STAG Set Tag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class STAG { adrs } Table 4–46 Table 4–46 Execution memory tag bit at address adrs PC + w Flags Affected None Opcode Instructions STAG { adrs }...
Page 266 Individual Instruction Descriptions 4.14.79 SUB Subtract Syntax [label] name dest, src , src1 , [ next A ]] Clock, clk Word, w With RPT, clk Class A n [~], A n , { adrs } [, next A ] Table 4–46 Table 4–46 A n [~], A n [~], imm16 [, next A ] A n [~], A n [~], PH [, next A ]...
Page 267 Individual Instruction Descriptions Syntax Description SUB A n [~], A n , { adrs } [, next A ] Subtract effective data memory word from A n [~], store result in A n SUB A n [~], A n [~], imm16 [, next A ] Subtract immediate word from A n [~], store result in A n [~] SUB A n [~], A n [~], PH [, next A ] Subtract Product High (PH) register from A n [~], store result in A n [~]...
Page 268 Individual Instruction Descriptions 4.14.80 SUBB Subtract Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SUBB A n , imm8 SUBB R x , imm8 Execution dest dest – imm8 PC + 1 Flags Affected dest is A n : OF, SF, ZF, CF are set accordingly dest is R x :...
Page 269 Individual Instruction Descriptions 4.14.81 SUBS Subtract Accumulataor String Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class SUBS A n [~], A n , { adrs } Table 4–46 Table 4–46 SUBS A n [~], A n [~], pma16 SUBS A n [~], A n , A n ~ SUBS...
Page 270 Individual Instruction Descriptions Syntax Description SUBS A n [~], A n , { adrs } Subtract data memory string from A n string, store result in A n [~] string SUBS A n [~], A n [~], pma16 Subtract program memory string from A n [~] string, store result in A n [~] string SUBS A n [~], A n , A n ~ Subtract A n ~ string from A n string, store result in A n [~] string SUBS A n [~], A n ~, A n...
Page 271 Individual Instruction Descriptions 4.14.82 SXM Set Extended Sign Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class Execution STAT.XM PC + 1 Flags Affected None Opcode Instructions Description Sets extended sign mode status register (STAT) bit 0 to 1. See Also Example 4.14.82.1 Set XM bit of STAT to 1.
Page 272 Individual Instruction Descriptions 4.14.83 VCALL Vectored Call Syntax [label] name dest Clock, clk Word, w With RPT, clk Class VCALL vector8 Execution Push PC + 1 *(0x7F00 + vector8 ) R7 + 2 Flags Affected None Opcode Instructions VCALL vector8 vector8 Description Unconditional vectored call (Macro call).
Page 273 Individual Instruction Descriptions 4.14.84 XOR Logical XOR Syntax [label] name dest, src, src1 [, mod ] Clock, clk Word, w With RPT, clk Class A n , { adrs } Table 4–46 Table 4–46 A n [~], A n [~], imm16 [, next A ] A n [~], A n ~, A n [, next A ] TF n , { flagadrs } TF n , { cc } [, R x ]...
Page 274 Individual Instruction Descriptions See Also XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NOTACS Example 4.14.84.1 XOR A1, A1, 0x13FF XOR immediate value 0x13FF to A1 and store result in A1. Example 4.14.84.2 XOR A0, A0, 2, ++A Pre–increment pointer AP0, then XOR immediate value 2 to new A0 and store result in A0. Example 4.14.84.3 XOR A1, A1~, A1 XOR accumulator A1 to accumulator A1~, put result in accumulator A1.
Page 275 Individual Instruction Descriptions 4.14.85 XORB Logical XOR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class XORB A n , imm8 Execution A n XOR imm8 (for two operands) PC + 1 Flags Affected dest is A n : OF, SF, ZF, CF are set accordingly Opcode Instructions...
Page 276 Individual Instruction Descriptions 4.14.86 XORS Logical XOR String Syntax [label] name dest, src [ , src1 ] Clock, clk Word, w With RPT, clk Class XORS A n , { adrs } Table 4–46 Table 4–46 XORS A n [~], A n [~], pma16 XORS A n [~], A n ~, A n Execution...
Page 277 Individual Instruction Descriptions 4.14.87 ZAC Zero Accumulator Syntax [label] name dest [ , mod ] Clock, clk Word, w With RPT, clk Class A n [~] [, next A ] Execution [premodify AP if mod specified] dest PC + 1 Flags Affected ZF = 1 Instructions...
Page 278 Individual Instruction Descriptions 4.14.88 ZACS Zero Accumulator String Syntax [label] name dest Clock, clk Word, w With RPT, clk Class Execution dest PC + 1 Flags Affected ZF = 1 Instructions ZACS A n [~] Description Zero the specified accumulator string. See Also Example 4.14.88.1 ZACS A1~...
Page 279: Instruction Set Encoding
Instruction Set Encoding 4.15 Instruction Set Encoding Instructions ADD A n [~], A n , { adrs } [, next A ] next A adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] ADD A n [~], A n [~], imm16 [, next A ] next A A~ ~A imm16...
Page 280 Instruction Set Encoding Instructions CMP A n , { adrs } adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] CMP A n [~], imm16 [, next A ] next A A~ ~A imm16 CMP A n , A n ~ [, next A ] next A CMP A n ~, A n [, next A ] next A...
Page 281 Instruction Set Encoding Instructions JMP pma16 , R x –– pma16 JMP pma16 , R x ++R5 pma16 JMP *A n J cc pma16 pma16 J cc pma16 , R x ++ pma16 J cc pma16 , R x –– pma16 J cc pma16 , R x ++R5 pma16...
Page 282 Instruction Set Encoding Instructions MOV PH, { adrs } adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MOV MR, { adrs } adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MOV AP n , { adrs } AP n adrs dma16 (for direct) or offset16 (long relative) [see section 4.13]...
Page 283 Instruction Set Encoding Instructions MOVB { adrs }, A n dma16 (for direct) or offset16 (long relative) [see section 4.13] MOVB A n , imm8 imm8 MOVB MR, imm8 imm8 MOVB R x , imm8 MOVBS A n , { adrs} adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MOVBS { adrs} , A n...
Page 284 Instruction Set Encoding Instructions MUL { adrs } adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MULR { adrs } adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MULS A n [~] MULAPL A n , { adrs } adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MULAPL A n [~], A n [~], [ next A ]...
Page 285 Instruction Set Encoding Instructions ORS A n [~], A n [~], pma16 A~ ~A ORS A n [~], A n ~, A n A~ ~A OUT port4 , { adrs } port4 adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] OUT port6 , A n [~] port6 OUTS port6 , A n [~]...
Page 286 Instruction Set Encoding Instructions SHLTPLS A n [~], A n [~] A~ ~A SHLAC A n [~], A n [~] [, next A ] next A A~ ~A SHLACS A n [~], A n [~] A~ ~A SHRAC A n [~], A n [~] [, next A ] next A A~ ~A SHRACS A n [~], A n [~]...
Page 287 Instruction Set Encoding Instructions ZAC A n [~] [, next A ] next A ZACS A n [~] cc names Description Tr e condition ( N t tr e condition) True condition ( Not true condition) cc name Not cc name Conditional on ZF=1 ( Not condition ZF=0) Conditional on SF=1 ( Not condition SF=0) Conditional on CF=1 ( Not condition CF=0)
Page 288: Instruction Set Summary
Instruction Set Summary 4.16 Instruction Set Summary Use the legend in Section 4.13 and the following table to obtain a summary of each instruction and its format. For detail about the instruction refer to the detail description of the instruction. name dest [, src] [, src1] [,mod] Clock, clk...
Page 289 Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk Class R x , imm16 A n [~], A n [~] [, next A ] A n [~], imm16 [, next A ] R x , R5 CMPB A n , imm8...
Page 290 Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk Class { adrs }, A n [~] [, next A ] Table 4–46 Table 4–46 A n [~], { adrs } [, next A ] Table 4–46 Table 4–46 { adrs }, *A n...
Page 291 Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk Class { adrs }, SV Table 4–46 Table 4–46 { adrs }, AP n Table 4–46 Table 4–46 { adrs }, TOS Table 4–46 Table 4–46 STR, { adrs } Table 4–46...
Page 292 Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk Class MOVU MR, { adrs } Table 4–46 Table 4–46 MOVAPH A n , MR, { adrs } Table 4–46 Table 4–46 MOVAPHS A n , MR, { adrs } Table 4–46 Table 4–46...
Page 293 Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk Class TF n , { flagadrs } TF n , { cc } [, R x ] A n , imm8 A n , { adrs } Table 4–46 Table 4–46 A n [~], A n [~], pma16...
Page 294 Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk Class A n , { adrs } SHLTPLS Table 4–46 Table 4–46 A n [~], A n [~] SHLTPLS SHLAC A n [~], A n [~] [, next A ] A n [~], A n [~] SHLACS SHRAC...
Page 295 Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk Class A n , { adrs } XORS Table 4–46 Table 4–46 XORS A n [~], A n [~], pma16 XORS A n [~], A n ~, A n A n [~] [, next A ] ZACS A n [~]...
Page 296 Instruction Set Summay 4-204 Assembly Language Instructions...
Page 297 Instruction Set Summay Assembly Language Instructions 4-205...
Page 298 Interrupt Vector Source Trigger Event Priority Comment INT0 0x7FF0 DAC Timer timer underflow highest used to synch. speech data 2 nd INT1 0x7FF1 TIMER1 timer underflow 3 rd INT2 0x7FF2 TIMER2 timer underflow 4 th INT3 0x7FF3 port PD2 rising edge port PD2 goes HIGH 5 th INT4...
Page 299 10 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference) ClkSpdCtrl ClkSpdCtrl Master Master Output Output Number of Number of Number of Number of IntGenCtrl IntGenCtrl PLLM PLLM Clock Clock Clock Clock Sampling Sampling Instructs Instructs Instructs Instructs Over-Sampling PDMCD Register Rate Rate Rate...
Page 300 Instruction Set Summay 4-208 Assembly Language Instructions...
Page 301: Code Development Tools
Chapter 5 Code Development Tools For code development purposes, the programmable MSP50P614 is used. The MSP50C6xx code development tool is used to compile, link, and debug assembly language programs. This tool can also be used to program an MSP50P614. A reduced function C compiler, (called C– –) is also available. Topic Page Introduction...
Page 302: Introduction
Introduction 5.1 Introduction The MSP50C6xx development tools gain access to the core controller via a serial scan interface called the Scanport. The basic elements needed to do de- velopment with the MSP50C6xx devices are listed below in Section 5.3. The MSP50C6xx software development tool is included with the MSP scanport in- terface (TI part #MSPSCANPORTI/F) or MSPSI.
Page 303: Level Translator Circuit
MSP50C6xx Software Development Tool the reset circuit and the reset pin, and connecting the scanport reset signal directly to the reset pin. See the recommended reset circuit shown in Figure 1–3. It is also recommended that all production boards be built with the scanport interface connector footprint connected to the appropriate pins and VPP-level translator circuit shown in Figure 5–1.
Page 304: Requirements
Requirements 5.3 Requirements The requirements for a complete MSP50C6xx development system are as follows: PC Requirements: Intel i486 or Pentium class processor Microsoft Windows 3.11, Windows 95 , or Windows 98 operating system 16-MB memory 8-MB hard disk space Parallel port interface Development Requirements: MSP50C6xx Scanport Interface (MSPSI) MSP50C6xx software development tool (Included with MSPSI)
Page 305: Hardware Installation
Hardware Installation 5.4 Hardware Installation The following steps are used to set up the hardware (see Figure 5–2): 1) Connect the 18 V power supply to the MSPSI and connect the mains pins to a 120 V, 60 Hz ac source. 2) Connect one end of the IEEE1284 parallel cable to the MSPSI board and the other end to the PC parallel port.
Page 306: Installshield Window
Software Installation Figure 5–3. 10-Pin IDC Connector (top view looking at the board) 10-PIN HEADER (3M PART# 2510–60024B) 0.35 IDC2X5M IDC2X5M V PP RESET PAD DIA 0.060 PGMPULSE SCANCLK SYNC 0.800 HOLE DIA 0.038 SCANIN SCANOUT V DD PINOUT DETAILS LAYOUT DETAILS 5.5 Software Installation Install the MSP50P614/MSP50C614 development tool from the supplied...
Page 307: Setup Window
Software Installation Figure 5–5. Setup Window Step 2: After setup runs the InstallShield (see Figure 5–4), the setup window pops up (see Figure 5–5). Step 3: Press the Next > button to continue with installation or press Cancel to exit installation. Code Development Tools...
Page 308: Exit Setup Dialog
Software Installation Figure 5–6. Exit Setup Dialog Step 4: If you press Cancel , you can return to setup by pressing Resume but- ton. You can exit setup by pressing Exit Setup button (Figure 5–6). Figure 5–7. User Information Dialog...
Page 309: Choose Destination Location Dialog
Software Installation Step 5: If you continue with setup, you will be brought to User Information dialog. Enter your Name and Company Name in the two respective fields. To get into this screen, you must press yes to the license screen and press next to the Information dialog.
Page 310: Select Program Folder Dialog
Software Installation Figure 5–9. Select Program Folder Dialog Step 9: Enter a new folder name in Select Program Folder dialog. Step 10: Press Next > to continue with installation. 5-10...
Page 311: Copying Files
Software Installation Figure 5–10. Copying Files Step 11: The program starts installation. When the installation is complete, an icon is also created on the desktop. Code Development Tools 5-11...
Page 312: Setup Complete Dialog
Software Installation Figure 5–11.Setup Complete Dialog Step 12: The Setup Complete dialog message is displayed when setup is completed. Press the Finish button to complete the installation. 5-12...
Page 313: Open Screen
Software Emulator 5.6 Software Emulator Run the EMUC6xx.exe program which will be in the installation directory or on your desktop (icon). Your scanport interface and the target board must be connected and turned on before the emulator can be successfully used. If the opening window comes up without any messages, the system is working properly.
Page 314: Project Menu
Software Emulator Figure 5–13. Project Menu Figure 5–14. Project Open Dialog 5-14...
Page 315: File Menu Options
Software Emulator Figure 5–15. File Menu Options 5.6.2 Projects The emulator can only work from project files created within the emulator itself. These files have the extension .rpj, and are not compatible with the .rpj files used in the old simulator . In other words, even to assemble a single as- sembly program, the user has to create a project and insert the name of the assembly file in the project.
Page 316: Msp50P614/Msp50C614 Code Development Windows
Software Emulator (pfe32.exe) and an error dialog. The user can modify the source code and save the changes, before restarting the building action. 5.6.3 Description of Windows Once a new project is created or an old project is opened, the following seven windows pops open (Figure 5–16).
Page 317: Ram Window
Software Emulator Figure 5–17. RAM Window RAM Window : Displays 16-bit data memory hex values. The left most column is the address. Data memory is always addressable as bytes by MSP50C614 instructions. Each value displayed in this window is actually two consecutive byte data.
Page 318: Cpu Window
Software Emulator Watch Window : Watch window displays the data memory location and data to be watched. It mirrors the value displayed in the RAM window. The Watch window is provided as a help to display locations that may not be visible in the RAM window without scrolling.
Page 319: Program Window
Software Emulator being run in emulation mode. STK field is the depth of the stack. The emulator keeps track of number of calls and returns and changes this variable accordingly. CUR field is the current subroutine name. In C–– programs it becomes very handy to display local variables of a subroutine.
Page 320: Hardware Breakpoint Dialog
Software Emulator background is the line reached by a search command (by PC, line number or label). Search position can also be set by double clicking on it in the program window. The line (if any) contain the hardware breakpoint is displayed in green background.
Page 321: Inspect Dialog
Software Emulator variable value and its address in RAM are then displayed (Figure 5–21). Variables appearing on a gray background either are not defined, or are not active at this time. The user can also use the Inspect option in the Debug menu to insert a variable in the Inspect window.
Page 322: I/O Ports Window
Software Emulator modified (i.e, by double clicking on a value and typing its new hexadecimal value over the existing value). Values of read only registers cannot be modified. Figure 5–23. I/O Ports Window Project Window : All source files making up the project are displayed in this window.
Page 323: Debug Menu
Software Emulator Step Over : This menu option, (key equivalent: F8), allows the user to step over a call instruction in the program window. Note that the program window does not need to have the focus to execute a Step instruction. If the Step Over instruction leads into a gray area , i.e., a program line, or group of program lines that cannot be stepped into, the system automatically execute the instructions until it gets out of the gray area.
Page 324 Software Emulator Fast Run : This menu option, (key equivalent: CTRL+F9), allows the user to execute a portion of the program window, until a breakpoint is encountered. The windows are not refreshed until the program stops, so that the execution speed is maximized.
Page 325: Eprom Programming Dialog
Software Emulator Figure 5–25. EPROM Programming Dialog Code Development Tools 5-25...
Page 326: Trace Mode
Software Emulator Trace Mode : This menu option launches the Trace Mode Dialog (Figure 5–25), that allows that user to run the chip in trace mode , i.e., running an internal program on the chip while monitoring its execution on the scanport. Figure 5–26.
Page 327: Init Menu Option
Software Emulator Stop Internal : This menu option halts execution of an internal program. It provides an internal picture of the chip at the time the internal program execution was halted. Note that due to the asynchronous nature of this halt, one erroneous instruction may be executed before the chip actually stops.
Page 328: Emulator Options
Software Emulator Init RAM : Initializes the data memory values to zero including tag bits. Init Registers : Initializes all the system registers (excluding accumulators) to zero except PC which is initialized to start vector. Init Accumulators : Initializes all the accumulators to zero. Init All : This menu option initializes all internal registers and all RAM location in the chip.
Page 329: Options Menu
Software Emulator Figure 5–28. Options Menu Figure 5–29. Miscellaneous Dialog List of directories separated by semicolons that the C–– compiler will search for include files enclosed in angle brackets (<>) before searching current directory. Heap start address for C–– compiler. Beginning of Stack for C––...
Page 330: Windows Menu Options
Software Emulator Figure 5–30. Windows Menu Options 5.6.7 Emulator Online Help System The emulator has an online help which is launched when the Help menu option is left clicked with a mouse. The help window (Figure 5–30) is context sensitive and graphical in nature.
Page 331: Context Sensitive Help System
Software Emulator Figure 5–31. Context Sensitive Help System Code Development Tools 5-31...
Page 332: Known Differences, Incompatibilities, Restrictions
Software Emulator 5.6.8 Known Differences, Incompatibilities, Restrictions Include statements in assembly language files must enclose the file name in double quotes. REF/DEF statements in assembly language files should be replaced with EXTERNAL/GLOBAL statements, but the old REF/DEF are still supported. There is no default type for variables in the C–...
Page 333: Assembler
Assembler 5.7 Assembler The MSP50P614/MSP50C614 assembler is implemented as a Windows DLL (Dynamic Linked Library). 5.7.1 Assembler DLL The current name of the DLL file is asm6xx.dll. It can be invoked from any Windows program, provided that the user included the file called asm6xx.lib in the Windows project.
Page 334: Assembler Directives
Assembler 5.7.2 Assembler Directives Assembler directives are texts which have special meaning to the assembler. Some of these directives are extremely helpful during conditional compiling, debugging, adding additional features to existing codes, multiple hardware development, code release etc. Other directives are an essential part of the assembler to initialize variable with values, assigning symbols to memory location, assigning origin of a program, etc.
Page 335 Assembler symbol is any alphanumeric text starting with an alphabetic character, a number, or an expression. Examples: SYM1 EQU (12 * 256) SYM2 EQU SYM1 * (32 / 4) SYM3 EQU SYM1 * SYM2 – *0x200 From the above example SYM1, SYM2 and SYM3 are symbols for some ex- pression.
Page 336 Assembler Example: #IF expression ; do something here #ELSE ; do other things here #ENDIF #IFDEF symbol: Start of a conditional assembly structure. If symbol has been defined (either with a #DEFINE directive or an EQU directive) then the lines following this directive are assembled until a #ELSE or a #ENDIF directive are encountered.
Page 337 Assembler BYTE expression[,expression]: Introduces one or more data items, of BYTE size (8 bits) . The bytes are placed in the program memory in the order in which they are declared. CHIP_TYPE chip_name: This directive is here for compatibility with future chips in the same family.
Page 338: Linker
Linker should be declared there as EXTERNAL (or REF). Note that this technique can also be used to make constants defined with the EQU statement available to other files. INCLUDE filename : This directive is used to insert another file in the current assembly file.
Page 339: C–– Compiler
C– – Compiler The syntax of the call is: extern int FAR PASCAL LINK_MAIN (LPSTR source_file,LPSTR exe_file); ..ierr=LINK_MAIN (source_file,exe_file); Where: source_file is the project file name, which contains the names of the files to be linked. exe_file is the name of the linked executable file. ierr is the total number of errors returned by the linker.
Page 340: Foreword
C– – Compiler short ram_size; /* ram size for the chip */ short verbose; /* refers to assembly code output */ short c_code; /* if non zero, c code is included as */ /* assembly language comments */ short optimize; /* should always be non zero */ char dir_list;...
Page 341: Variable Types
C– – Compiler 5.9.2 Variable Types Type Name Mnemonic Range Size in Bytes Example Integer [–32768,32767] 2 int i,j; Character char [0,255] char c,d; Array of integer Not Applicable Not Applicable int array[12]; Array of characters char Not Applicable forced to even char text[20] Pointer to integer int *...
Page 342: C– – Directives
C– – Compiler 5.9.4 C– – Directives C– – has a limited number of directives and some additional directives not found in ANSI C compilers. The following directives are recognized by the compiler. 5.9.4.1 #define This directive is used to introduce 2 types of macros, in typical C fashion: Without Arguments: defines a replacement string for a given string Example:...
Page 343 C– – Compiler 5.9.4.3 #include As in regular C, this directive allows for the insertion of a file into the current file. If the file name that follows is enclosed in < >, the system searches the include directories for the file, otherwise, if it is enclosed in “ ”, the current directory is searched.
Page 344: Include Files
C– – Compiler 5.9.5 Include Files There are currently two include files supplied with C– –, cmm_func.h, which contains function prototypes for the C– –functions and cmm_macr.h which contains some predefined macros. Both files are listed below: /********************************/ /* Prototypes for C– –functions */ /********************************/ cmm_func add_string(int *result,int *str1,int *str2,int lg);...
Page 345: Function Prototypes And Declarations
C– – Compiler 5.9.6 Function Prototypes and Declarations As mentioned above, C– – function prototypes and declarations MUST be preceded with the keyword cmm_func. Also, since all functions return through accumulator A0, all functions are of type integer, so that the function type can be omitted in the function declaration.
Page 346: String Functions
C– – Compiler Table 5–1. String Functions add_string(int *result,int *str1,int *str2,int lg)adds strings str1 and str2, of length lg (+2), and puts the result in string result sub_string(int *result,int *str1,int *str2,int lg) subtracts strings str2 from str1, of length lg (+2), and puts the result in string result.
Page 347: Constant Functions
C– – Compiler Also note that the user has to supply the length of the input string and the length of the output string in the string multiply operations: the result of multiplying a string by an integer can be one word longer than the input string. Unpredictable results may occur if parameter lgr is not at least equal to lgr+1.
Page 348: Implementation Details
Implementation Details 5.10 Implementation Details This section is C– – specific. 5.10.1 Comparisons We use the CMP instruction for both signed and unsigned comparisons. The two integers a and b to be compared are in A0 and A0~. CMP A0,A0~ : A0 contains a, A0~ contains b ANEG FFFF FFFF...
Page 349 Implementation Details Unsigned comparison of a and b. (a is in A0, b is in A0~) Assembly Test Condition _ult a < b AULT _ule a <= b !AUGT _uge a >= b !AULT _ugt a > b AUGT The small number of comparisons was an invitation to use them as vector calls.
Page 350: Division
Implementation Details 5.10.2 Division The integer division currently requires the use of several accumulator pointers. We divide a 16 bit integer located in A0 by a 16 bit integer located in A0~. We return the quotient in A0~, and the remainder in A0. We make use of A3~ and A3 for scratch pads.
Page 351: Programming Example
Implementation Details Function declarations ( or function prototypes) are introduced by the mnemonic cmm_func. We only allow the new style of function declarations /prototypes, where the type of the arguments is declared within the function’s parentheses. For example: cmm_func bidon(int i1,char *i2) is valid, but: cmm_func bidon(i1,i2) int i1,char *i2;...
Page 352 Implementation Details constant int M1[4]={0x04CB,0x71FB,0x011F,0x0}; constant int M2[4]={0x85EB,0x8FD9,0x08FB,0x0}; cmm_func string_multiply(int *p,int lgp,int *m1,int lgm1,int *m2,int lgm2) /* note: length of p,(lgp+2) must be at least (lgm1+2) + (lgm2+2) +1 */ /* this function string multiplies string m1 of length lgm1+2 by string m2 of length lgm2+2, and puts the result into string p, of length lgp+2 */ int sign,i,j;...
Page 353: Programming Example, C – With Assembly Routines
Implementation Details free(mm2); free(pp); cmm_func main(int argc,char *argv) int m1[4],m2[4],product[9]; xfer_const(m1,M1,STR_LENGTH(4)); xfer_const(m2,M2,STR_LENGTH(4)); string_multiply(product,STR_LENGTH(9),m1,STR_LENGTH(4),m2,STR_LENGTH(4)); 5.10.5 Programming Example, C –– With Assembly Routines There are several important considerations when using the C– – compiler. The ram allocation must be coordinated so that a location is not accidentally used twice.
Page 354 Implementation Details find the correct size for bogus. Bogus can be made larger for extra safety as long as enough memory is left over for the C– – variables and the stack. If space allows, it is a good idea to add a few extra words to bogus in case assembly variables are added to the project without modifying bogus.
Page 355 Implementation Details |––––––––––––––| |––––––––––––––| |––––––––––––––| |R7 | |R5,R7 | |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |(old)R5 |<– This is the SP |––––––––––––––| |––––––––––––––| |––––––––––––––| before the |(old)R5 |C function call. |––––––––––––––| |––––––––––––––| |––––––––––––––| R7 |Return Addr |Return Addr |Return Addr |––––––––––––––| |––––––––––––––| |––––––––––––––|...
Page 356 Implementation Details C to C function return (in cmm_return). |––––––––––––––| |––––––––––––––| |––––––––––––––| R5 | |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| R7 |(old)R5 |(old)R5 |(old)R5 |––––––––––––––| |––––––––––––––| |––––––––––––––| |(old)R5 |(old)R5 |(old)R5 |––––––––––––––| |––––––––––––––| |––––––––––––––| |Return Addr |R7 |Return Addr |Return Addr |––––––––––––––| |––––––––––––––| |––––––––––––––|...
Page 357 Implementation Details |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |(old)R5 |––––––––––––––| |(old)R5 |––––––––––––––| |Return Addr |––––––––––––––| |Return Addr |––––––––––––––| |Param 2 |––––––––––––––| |Param 2 |––––––––––––––| |Param 1 |––––––––––––––| |Param 1 |––––––––––––––| R7,R5 |Stack data |––––––––––––––| SUBB R7,4 Code Development Tools 5-57...
Page 358 Implementation Details C to ASM function call. The stack is shown after the operation on the bottom is performed. |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |R7 |Param 2 |––––––––––––––| |––––––––––––––|...
Page 359 Implementation Details |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |Return Addr |––––––––––––––| |Return Addr |––––––––––––––| |Param 2 |––––––––––––––| |Param 2 |––––––––––––––| |Param 1 |––––––––––––––| |Param 1 |––––––––––––––| |Stack data |––––––––––––––| Function call C to ASM function return |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––|...
Page 360 Implementation Details To call an assembly routine from C– –, the routine must be defined as GLOBAL in the assembly file and as a CMM_FUNC in the C– – file. The following contains C– – callable assembly routines for accessing the I/O ports, and a wait routine.
Page 361 Implementation Details ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ; called from C–– ; void oport(char Port, int Data) ; Writes Data to the I/O port specified by the letter Port. ; Example: oport(’B’, 0xAA); //Write 0xAA to port B. ;––––––––––––––––––––––––––––––––––––––––––––––––––––– _oport a0, *r7 – 4 ;...
Page 362 Implementation Details _iprtc a0, 0x10 ; read from PortC _iprtd a0, 0x18 ; read from PortD _iprte a0, 0x20 ; read from PortE _iprtf a0, 0x28 ; read from PortF _in_port_access ; table for table lookup DATA _iprta DATA _iprtb DATA _iprtc DATA...
Page 363 Implementation Details DATA _cprte ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ; called from C–– ; void wait(int msec) ; waits for the amount of msec passed ; Calls: wait1ms ;––––––––––––––––––––––––––––––––––––––––––––––––––––– _wait a0, *r7 – 2 shlac a0, a0 *tempa, a0 r4, *tempa _rep call wait1ms ;wait 1ms jrnzp _rep,r4––...
Page 364 (MS7 and MS8 simultaneously for ex- ample ) or by only indicating an incorrect code after the sequence is com- plete. #Revisions: #Copyright: (c) Copyright 1999 Texas Instruments, Inc. All Rights Reserved #******************************************************************************* #endif #include ”ram\ram.h” cmm_func asminit();...
Page 365 Implementation Details cmm_func iport(int x); // read a port int i,j,k,l; // various temp and loop variables int x[4]; // array holding the correct key sequence int locked=1; //variable returned by lock() cmm_func lock(){ x[0]= 0xEF; //MS7 x[1]= 0xBF; //MS9 x[2]= 0xEF;...
Page 366 Implementation Details wait(100); oport(’B’, 0x00); wait(100); oport(’B’, 0xFF); wait(100); oport(’B’, 0x00); wait(100); oport(’B’, 0xFF); wait(100); else{ // If the correct inputs were given. oport(’B’,0x00); // Light all LED’s wait(5000); // Keep lit for 5 seconds ( unlock the door ) } // end for return;...
Page 367: Beware Of Stack Corruption
Beware of Stack Corruption 5.11 Beware of Stack Corruption MSP50C614/MSP50P614 stack (pointed by R7 register) can easily get cor- rupted if care is not taken. Notice the following table read code: SUBB R7, 4 MOV A0, *R7–– ADD A0, address MOV A0, *A0 ADD A0, *R7––...
Page 368 5-68...
Page 369: Applications
....6–4 Texas Instruments C614 Synthesis Code ......
Page 370: Application Circuits
Application Circuits 6.1 Application Circuits Minimum Circuit Configuration for the C614/P614 Using Resistor-Trimmed Oscillator † To pin 1 of Scan Port Connector (optional ) † To pin 2 of Scan Port Connector 0.1 F † 1N914 (optional ) (MSP50P614 only) 1N914 100 k RESET...
Page 371 Application Circuits It is of particular importance to provide a separate decoupling capacitor for the pair which services the DAC. These pins are pad numbers 21 and 19, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement. An alternate circuit, for better clock-precision and better battery life, includes a crystal oscillator: Minimum Circuit Configuration for the C614/P614 Using Crystal-Referenced Oscillator...
Page 372: Msp50C614/Msp50P614 Initialization Codes
MSP50C614/MSP50P614 Initialization Codes In any C614 application, it is important for certain components to be located as close as possible to the C614 die or package. These include any of the decoupling capacitors at V (0.1 F). It also includes all of the components in the crystal-reference network between OSC and OSC (22 pF, 10 M ,...
Page 373: File Init.asm
This Initialization Routine has the following Dependent Files. These should be ”included” once within the MAIN program .ASM file: IMPORTANT: Texas Instruments reserves the right to change this routine at any time without notice. ; ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– This Initialization Routine performs the following Functions: 1.
Page 374 MSP50C614/MSP50P614 Initialization Codes IntGenCtrl,a0 ;clear all interrupt mask bits, disable timers r0,0x000 ;point to beginning of RAM r4,RAM_SIZE – 2 ;do a loop RAM_SIZE times BEGLOOP rtag ;reset tag *r0++,a0 ;clear the RAM ENDLOOP STR,0 ;clear string register ap0,0 ;clear accum pointer 0 ap1,0 ;clear accum pointer 1 ap2,0...
Page 375 MSP50C614/MSP50P614 Initialization Codes *save_clkspdctrl,a0 ;save the ClkSpdCtrl value for later, when ;waking up from mid or deep sleep 0~,TIM2REFOSC + TIM2IMR ;disable TIMER 2 IntGenCtrl,a0~ a0~,6553 ;setup a 200 ms period TIM2,a0~ ;load TIM2 and PRD2 in one fell swoop a0~,TIM2ENABLE + TIM2REFOSC + TIM2IMR IntGenCtrl,a0~ ;use 32 kHz crystal as source, wake up...
Page 376: Texas Instruments C614 Synthesis Code
Texas Instruments C614 Synthesis Code 6.3 Texas Instruments C614 Synthesis Code Some sample codes are supplied with the development tools. These samples are in the .\Examples subdirectory where the tool is installed. In this manual only one example code is explained. This description applies to all the code development.
Page 377 Texas Instruments C614 Synthesis Code To continue, click on the Run Internal icon again. The LEDs should flash during MELP synthesis ( Extra, extra, read all about it ) and should flash in a different pattern after MELP synthesis. Running the Program The MELP1 program can run on either the demo box or the code development board.
Page 378 Texas Instruments C614 Synthesis Code spk_ram.irx –––––––– melp melp.obj melp.irx –––––––– modules –––––––– 605 605.asm 605.irx –––––––– general init.asm sleep.asm io_ports.irx –––––––– isr dac_isr.asm tim1_isr.asm tim2_isr.asm –––––––– ram ram.irx –––––––– speech –––––––– melp 1kbps.qfm 24kbps.qfm main.asm main.irx main_ram.irx melp1.rpj 6-10...
Page 379 Texas Instruments C614 Synthesis Code File Description Util.obj Maths functions and tables used by the vocoders. Dsputil.asm Oversampling and miscellaneous functions. Getbits.asm Routine to get data from ROM. Speak.asm Routines to speak a phrase or sentence. Dsp_var.irx Various vocoder constants.
Page 380 Texas Instruments C614 Synthesis Code RAM Usage The file MAIN.LST contains the variable RAM assignments. Do a search for BEGIN_RAM to find the start of the RAM locations. Adding Another Module There are three steps to adding a new module to a project. First, the project file (.RPJ) must be updated to include the ASM file (click on File –...
Page 381: Memory Overlay
Texas Instruments C614 Synthesis Code These files may be edited for special purpose code INIT.ASM and SPEAK.ASM These files should never be edited SLEEP.ASM, RAM.IRX and SPK_RAM.IRX A good rule of thumb to follow is that files under the DSP directory should be left alone, and all custom code should be added either to MAIN.ASM or to a...
Page 382: Rom Usage With Respect To Various Synthesis Algorithms
ROM Usage With Respect to Various Synthesis Algorithms 6.4 ROM Usage With Respect to Various Synthesis Algorithms The following table lists some possible synthesis options and their ROM requirements. The models assume that just enough program space, as necessary for storage of the synthesis algorithm, is used. The remainder of the ROM is dedicated entirely to the speech data, with the goal of maximizing the synthesis playback time.
Page 383: Customer Information
Chapter 7 Customer Information Customer information regarding package configurations, development cycle, and ordering forms are included in this chapter. Topic Page Mechanical Information ........7–2 Customer Information Fields in the ROM .
Page 384: Scan Port Bond Out
10 k resistor which appears at the RESET pin is optional. It is required for use with the Scan Port Interface, but they may be shorted otherwise. The footprints for this resistor is strongly recommended. 7.1.1 Die Bond-Out Coordinates Die bond-out coordinates are available upon request from Texas Instruments.
Page 385: Msp50C614 100-Pin Pjm Plastic Package Pinout Description
Mechanical Information 7.1.2 Package Information The MSP50C614 will be available in the 100-pin PJM package (see Figure 7–1 and Table 7–1). Contact your local TI sales office for more informa- tion. Table 7–1. MSP50C614 100-Pin PJM Plastic Package Pinout Description Description Pin # Description...
Page 386 Mechanical Information Figure 7–1. 100-Pin PJM Mechanical Information 0,38 0,65 0,13 0,22 14,20 17,45 12,35 TYP 13,80 16,95 18,85 TYP 20,20 19,80 23,45 0,16 NOM 22,95 Gage Plane 0,25 2,90 0,25 MIN 0 – 7 2,50 1,03 0,73 Seating Plane 0,10 3,40 MAX 4040022 / B 03/95...
Page 387 Mechanical Information The C614 is sold in die form for its volume production. For software develop- ment and prototyping, a windowed ceramic 120 pin grid array packaged P614 is available. The P614’s PGA package is shown in Figure 7–2. Figure 7–2. 120-Pin Grid Array Package for the Development Device, P614 extra pin 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9...
Page 388: Pin Grid Array (Pga) Package Leads, P614
Mechanical Information The pin assignments for the 120-pin PGA are outlined in the following table. (Refer to Section 1.6 for more information on the signal functions.) Figure 7–3 provides a cross-reference between the C614 (die) pad numbers and the P614’s PGA package leads. Figure 7–3.
Page 389: Customer Information Fields In The Rom
Customer Information Fields in the ROM 7.2 Customer Information Fields in the ROM In those cases where the customer code is programmed by Texas Instruments, some registration of the code-release is provided within the ROM. This information appears as 7 distinct fields within the ROM test-area. The ROM test-area extends from address 0x0000 to 0x07FF.
Page 390: Speech Development Cycle
Speech Development Cycle 7.3 Speech Development Cycle Figure 7–4. Speech Development Cycle Speech Specification Recording Script Software Design Hardware Design Speaker Selection Preparation Prototype Construction Speech Recording Software Writing Speech Analysis Software Debugging Speech Editing Speech Evaluation System Evaluation A sample speech development cycle is shown in Figure 7–4. Some of the com- ponents, such as speech recording, speech analysis, speech editing, and speech evaluation, require different hardware and software.
Page 391 Customer verification Texas Instruments recommends that prototype devices not be used in produc- tion systems. The expected end-use failure rate of these devices is undefined; however, it is predicted to be greater than that of the standard qualified produc- tion.
Page 392: Ordering Information
Ordering Information 7.5 Ordering Information Because the MSP50C614 is a custom device, it receives a distinct identifica- tion, as follows: Revision Package or Die Gate Code Family Letter PJM: Loopin QFP CSM: Custom Member Code (Preliminary) Synthesizer Y: Die With Memory 7.6 New Product Release Forms The new product release form is used to track and document all the steps in- volved in implementing a new speech code onto one of the parent speech de-...
Page 393 I authorize TI to start normal production in accor- dance with purchase order #______________________. By:_____________________________________________ Title:__________________________________________ Date________________ ************************************************************************ Return to: Texas Instruments Incorporated Attn: Code Release Team P.O. Box 660199, M/S 8718 Dallas, TX 75266–0199 OR Fax to: (972)480–7301 Attn: Code Release Team...
Page 394 7-12...
Page 395: Msp50C605
Appendix A Appendix A MSP50C605 Preliminary Data This Appendix contains preliminary data for the MSP50C605 device. Note: MSP50C605 MSP50C605 is in the Product Preview stage of development. For more in- formation contact your local TI sales office. Topic Page Introduction .
Page 396: A.1 Introduction
Introduction A.1 Introduction MSP50C605 is a spin off of the core processor MSP50C614. It uses three IO ports of MSP50C614 and maps a 1.835 Mbits of internal ROM. Using a 1 kbps MELP algorithm, the C605 can provide over 30 minutes of uninterrupted speech.
Page 397: A.3.1 Ram
ROM space is divided into three areas: 1) The initial 2K words of ROM (0x0000 – 0x07FF) is reserved for built in self- test (BIST) that is provided by Texas Instruments during mass production. 2) Customer can use the program ROM from address extending from 0x0800 to 0x7FFF.
Page 398: Msp50C605 Architecture
Architecture Figure A–1. MSP50C605 Architecture V SS V DD V PP Scan Interface SCAN IN Power (P614 only) SCAN OUT Data ROM Break Point 229,376 x 8 bit (EP) ROM 32k x (16 + 1) bit Emulation SCAN CLK OTP Program Test–Area 0x0000 to Serial Comm.
Page 399: Msp50C605 Memory Organization
Architecture Figure A–2. MSP50C605 Memory Organization Program Memory Data Memory Peripheral Ports 0x 00 0x0000 0x 0000 0–7 Internal Test Code 0x 08 0–3 2048 x 17 bit 640 x 17 bit 0x 10 data 0..7 0x 027F 0x 14 ctrl (reserved ) 0..7...
Page 400: Msp50C605 100-Pin Pjm Package
Architecture Figure A–3. MSP50C605 100-Pin PJM Package MSP50C605 100 PIN PJM PLASTIC PACKAGE...
Page 401: Msp50C605 100-Pin Pjm Plastic Package Pinout Description
Architecture Table A–1. MSP50C605 100-Pin PJM Plastic Package Pinout Description Description Pin# Description Pin# Description Pin# Description Pin# DACM VCC3 DACP VCC1 SCAN_OUT TEST SYNC SCNCLK SCANIN INITZ VCC2 GND3 MSP50C605 Preliminary Data...
Page 403: Msp50C604
Appendix B Appendix A MSP50C604 Preliminary Data This Appendix contains preliminary data for the MSP50C604 device. Note: MSP50C604 MSP50C604 is in the Product Preview stage of development. For more in- formation contact your local TI sales office. Topic Page Introduction .
Page 404: B.1 Introduction
Introduction B.1 Introduction MSP50C604 is a spin off of the core processor MSP50C614. It is targeted as a slave device. An external microprocessor is needed to interface with MSP50C604 in slave mode. It can also be used a stand alone device if desired. B.2 Features 30k word ROM customer program memory 8 MHz uDSP core...
Page 405: B.3.1 Ram
ROM space is divided into two areas: 1) The initial 2K words of ROM (0x0000 – 0x07FF) is reserved for built in self- test (BIST) that is provided by Texas Instruments during mass production. 2) Customer can use the ROM from address extending from 0x0800 to 0x7FFF.
Page 406: Msp50C604 Block Diagram
Architecture Figure B–1. MSP50C604 Block Diagram V SS V DD V PP Scan Interface SCAN IN Power (P614 only) SCAN OUT Break Point (EP) ROM 32k x (16 + 1) bit Emulation SCAN CLK OTP Program Test–Area 0x0000 to Serial Comm. (reserved) 0x07FF SYNC...
Page 407: B.3.4 Slave Mode Operation
Architecture B.3.4 Slave Mode Operation The MSP50C604 is used as a peripheral device in slave mode. A microproces- sor/microcontroller controls the R/WZ, STROBE, INRDY, OUTRDY pins of MSP50C604 to use it as a slave processor. No special programming is re- quired to switchthe ’C604 to slave mode.
Page 408: Msp50C604 Memory Organization And I/O Ports
Architecture Figure B–2. MSP50C604 Memory Organization and I/O ports Program Memory Data Memory Peripheral Ports 0x0000 0x 0000 Internal Test Code 2048 x 17 bit 640 x 17 bit 0x 10 data 0..7 0x 027F 0x 14 ctrl (reserved ) 0..7 0x07FF 0x 18...
Page 409 Architecture B.3.7 Interrupts Interrupts for MSP50C604 are the same as MSP50C614 in host mode except INT5 (port F interrupt) is not available. But in slave mode, INT3 and INT4 are external interrupts triggered by write sequence and read sequence as ex- plained before.
Page 410: Msp50C604 64-Pin Pjm Plastic Package Pinout Description
Packaging B.4 Packaging The MSP50C604 is sold in die form. A 64 pin plastic package is also available. Table B–1. MSP50C604 64-Pin PJM Plastic Package Pinout Description Description Pin# Description Pin# Description Pin# Description Pin# VCC3 TEST SCAN_OUT SYNC SCAN_CLK SCAN_IN RESET VCC1...
Page 411: Msp50C604 Slave Mode Signals
Packaging Figure B–3. MSP50C604 Slave Mode Signals Host read Host write sequence sequence INRDY OUTRDY R/WZ STROBE Valid Data –PC New Data Data latched to Port A Figure B–4. MSP50C604 64-Pin PJM Package MSP50C604 64 PIN PJM PLASTIC PACKAGE MSP50C604 Preliminary Data...
Page 412 Packaging B-10...
Page 413 Appendix C Appendix A MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed-signal pro- cessor. Topic Page MSP50C605 Data Sheet ........C–2...
Page 414 C.1 MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed-signal pro- cessor.

Texas Instruments MSP50C614 User Manual

Table of Contents

2 MSP50C614 Architecture

3 Peripheral Functions

Assembly Language Instructions

5 Code Development Tools

7 Customer Information

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