External Interface Ready-On-Read Timing With One External Wait State; External Memory Interface Read Switching Characteristics (Ready-On-Read, 1 Wait State); External Memory Interface Read Timing Requirements (Ready-On-Read, 1 Wait State); Synchronous Xready Timing Requirements (Ready-On-Read, 1 Wait State) - Texas Instruments SM320F2812-HT Data Manual

SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011

6.25 External Interface Ready-on-Read Timing With One External Wait State

Table 6-37. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
t Delay time, XCLKOUT high to zone chip-select active low
d(XCOH-XZCSL)
t Delay time, XCLKOUT high/low to zone chip-select inactive high
d(XCOHL-XZCSH)
t Delay time, XCLKOUT high to address valid
d(XCOH-XA)
t Delay time, XCLKOUT high/low to XRD active low
d(XCOHL-XRDL)
t Delay time, XCLKOUT high/low to XRD inactive high
d(XCOHL-XRDH
t Hold time, address valid after zone chip-select inactive high
h(XA)XZCSH
t Hold time, address valid after XRD inactive high
h(XA)XRD
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-38. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
t Access time, read data from address valid
a(A)
t Access time, read data valid from XRD active low
a(XRD)
t Setup time, read data valid before XRD strobe inactive high
su(XD)XRD
t Hold time, read data valid after XRD inactive high
h(XD)XRD
(1) Not production tested.
(2) LR = Lead period, read access. AR = Active period, read access. See
Table 6-39. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
t Setup time, XREADY (Synch) low before XCLKOUT high/low
su(XRDYsynchL)XCOHL
t Hold time, XREADY (Synch) low
h(XRDYsynchL)
t Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
e(XRDYsynchH)
t Setup time, XREADY (Synch) high before XCLKOUT high/low
su(XRDYsynchH)XCOHL
t Hold time, XREADY (Synch) held high after zone chip select high
h(XRDYsynchH)XZCSH
(1) Not production tested.
(2) The first XREADY (Synch) sample occurs with respect to E in
E = (XRDLEAD + XRDACTIVE) t
When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is
sampled again each t
c(XTIM)
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) t
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
t Setup time, XREADY (Asynch) low before XCLKOUT high/low
su(XRDYAsynchL)XCOHL
t Hold time, XREADY (Asynch) low
h(XRDYAsynchL)
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT
t
e(XRDYAsynchH)
edge
t Setup time, XREADY (Asynch) high before XCLKOUT high/low
su(XRDYAsynchH)XCOHL
(1) Not production tested.
(2) The first XREADY (Asynch) sample occurs with respect to E in
E = (XRDLEAD + XRDACTIVE – 2) t
When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it wis
sampled again each t
c(XTIM)
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) t
where n is the sample number: n = 1, 2, 3, and so forth.
122 Electrical Specifications
PARAMETER
c(XTIM)
until it is found to be high.
– t
c(XTIM) su(XRDYsynchL)XCOHL
c(XTIM)
until it is found to be high.
– t
c(XTIM) su(XRDYasynchL)XCOHL
Submit Documentation Feedback
Product Folder Link(s):
Table 6-25.
Figure 6-31:
Figure 6-32:
Copyright © 2009–2011, Texas Instruments Incorporated
SM320F2812-HT
www.ti.com
MIN MAX
1
–2 3
2
1
–2 1
(2)
(2)
MIN MAX UNIT
(2)
(LR + AR) – 14
(2)
AR – 12
12
0
(1) (2)
MIN MAX
15
12
3
15
0
(1) (2)
MIN MAX UNIT
11
8
3
11
(1)
UNIT
ns
ns
ns
ns
ns
ns
ns
(1)
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns