Epson LQ-2550 Technical Manual page 92

2 . 3 . 1 . 3 INIT Signal Input from CN1 or CN2
Figures 2-36 shows the reset circuit and Figure 2-39 show the timing of the signals during this operation.
When the INIT signal is input from outside (it should be low for 50 PS or more), it reduces the voltage
at the CPU terminal via the integration circuit (R 115, C67, and D 13), the M546 10P (1 1 B), and IC (6 B).
When the voltage at the CPU terminal reaches VN, the reset circuit (in the MMU) is activated to set the
signal low. When the DISC signal goes low, the ROUT signal subsequently goes low, the voltage
DISC
at the THLD terminal drops
goes high after the reset circuit is initialized. When the THLD terminal voltage increases to VP, the ROUT
signal goes high again.
CPU
DISC
ROUT
to V (the pulse width shold be: TR2 > INIT = low), and then the DISC signal
N
5 ( v )
VP
VP
1
I
1
Figure 2-39. INIT Reset Timing
2-45
REV.-A