REV.-A
2.3 CONTROL CIRCUIT BOARD (ROMA Board)
Figure 2-33 shows a block diagram of the ROMA board.
The ROMA board mainly consists of two 8-bit CPUS; one is the HD64 180R 1 P6 (1 3A) for the main control
and the other is the pPD78 10HG (7B) for the sub control. Both are operated at a clock frequency of
12.2 MHz (to match the serial data transfer clocks). The main and sub CPUS communicate with each
other using serial ports. Various gate array ICS and hybrid ICS are employed to lighten the load on the
main and sub CPUS and to simplify the circuits.
I
8-BIT
— M5461OP
PARALLEL
l/F
I
PRINTER
MECHANISM
(
I
I
C .
I
—
12.2 MHZ
MMU
1
)0- 07
MM102
LATCH
(14C)
MM1OO
MM101
, ; :' ~
(2A)
(1A)
ROM
—
ROM
—
FONT I
—
( S L O T 81 ~ —
Figure 2-33. ROMA Board Block Diagram
—
B O A R D
—
1 2.2 MHZ
"
p o R T
P
- 7 P O O - 7 1 E
LATCH
1
I
2-40
—
—
1
ORIVER
LO SOLENOID
RL SOLENOIO
I
CR HP SENSOR
PE SENSOR
LO SENSOR
RL SENSOR
PRINTER
MECHANISM
THERMISTOR
R
—
J