Epson LQ-2550 Technical Manual page 121

2.3.5.1 E05A02LA Gate Array (2A)
Refer to Appendix A.1 .1.18 for the details of the E05A02 LA.
The E05A02LA gate array is a 24-pin printhead data control IC, and includes the interface circuits used
between the CPU and printhead driver. Because the gate array is mapped so that it corresponds to CPU
memory addresses, the functions of the gate array can be accessed as memory-mapped 1/0. This IC
constructs the data for one character row (24 dots) by inputting 8-bit data three times, and outputs the
print signal to printhead driver IC STK66082E (1A) using printhead trigger pulse HPW. The IC also has
functions to write and output the 24-bit data effectively. Table 2-48 shows the E05A02LA gate array
functions.
Address Bus AO
o
1
NOTE: When HPW is set invalid, the output is open-drain active regardless of the HPW input.
Table 2-48. E05A02LA Gate Array Functions
Inputs a command.
Data bit 7:
Data bit 6:
Data bit 5:
Data bits 4 to O:
Latches data, and increments the counter.
When latching data, half-protection is performed by NANDing the contents
of the new data and the previous data (so that the output goes LOW
continuously).
. Data latching is completed by latching l-byte data three times.
The REDY signal is changed to HIGH by the WR signal that latches the third
byte, so that data transfer is automatically inhibited.
When HPW is set valid, the latched data is inverted and output while HPW
LOW.
is
The REDY signal goes LOW at the leading edge of HPW, to indicate that the
gate array is ready to receive data.
Function
Sets the data latch write sequence.
HIGH: Ascending order
LOW: Descending order
Enables/disables the HPW.
Resets the counter.
Not used.
2-75
REV.-A