Epson LQ-2550 Technical Manual page 144

REV.-A
2.3.8 PG and CS Motors Control/Drive Circuits
Figure 2-89 shows a block diagram of the PG motor and CS motor drive circuits.The MCU (3B) is mapped
into the sub CPU address space, and the PG and CS motors are controlled from the sub CPU by sending
commands to the MCU (3 B).The reference clock required to generate phase switching pulses for the
stepper motor drive is generated by the timer within the sub CPU, which generates the phase switching
pulses for the PG and CS motor drive circuits by sending commands to the MCU.
The PG and CS motors are driven using constant voltage.
+ 3 5 + 5 Vx
1
PG MOTOR
PG
DRIVER
MOTOR
CIRCUIT
1
GH
+35 +5
A A
I
Cs
DRIVER
MOTOR CIRCUIT
(CS UNIT)
GH
Figure 2-89. PG and CS Motors Drive Circuits Block Diagram
HOLD\ DRIVE
c
PHASE PULSES
I
A
1
HOLD/DRIVE
c
PHASE PULSES
I
ADDRESS
AO1
DO1
ADO
LOW ADDRESS
1
LATCH (8A)
3
MSU
I
(3 B)
D02
I
.
L
2-98
PF6
1
( 6 A ) 7
ALE
SUB CPU
PDO
1
7
c ~R
I
(7 B)