Epson LQ-2550 Technical Manual page 255

Timing
Three oscillator cycles define one state.
One read/write machine cycle requires three states, and one OP code fetch machine cycle requires
4 states.
Wait states cannot be inserted.
OP Code Fetch Timing
a)
The OP code fetch timing consists of four states, T1 to T4. During T1 to T3, program memory is
read, and instructions are processed (decoded) during T4.
AB 15 to 8 (PF7 to O) are output from T1 to T4. Since AD7 to O (PD7 to O) are used in the multiplex
mode, the address is latched at the ALE signal during state T1, and the drivers for AD7 to O are
disabled. Then the ~ signal is output from T1 to T3 to enable the memory to be addressed, fetching
at T3, and internal processing at T4.
CLOCK
ALE
AB15 -8
b) Memory Read Timing
The memory read timing consists of three states, T1 to T3.
Timings for address output, the ALE signal, and the ~ signal are the same as those for the OP code
fetch (excluding T4).
CLOCK
AB15 -8
Y
x
A D D R E S S }- --<
Figure A-7. OP Code Fetch Timing
T1
ALE
A D D R E S S ~ --- -(
Figure A-8. Memory Read Timing
ADDRESS
OP CODE
T2
ADDRESS
READ DATA
A-1 O
T3
x