Epson LQ-2550 Technical Manual page 130

2.3.7.2 CR Motor Control/Drive Circuit
The circuits included in the CR motor control/drive circuit are as follows.
Figure 2-78 shows the TM 1 clock generation circuit and Figure 2-79 shows the timing for the sub CPU
output signal and TM 1 signal. This circuit employs retriggerable IC LS 123 (5A). This IC generates the
TM 1 signal that includes a constant LOW pulse width even when the frequency of the reference clock
output from the TO terminal of the sub CPU changes (when acceleration, deceleration, or constant speed
control is performed.) The LOW pulse width is set to approximately 25 [ps] by R25 and C 13.
NOTE: In the
Figure 2-79. Sub CPU Output Signal and TM1 Signal T
MCU \
+5
Figure 2-78. TM1 Clock Generation Circuit
TO
test mode: T1 = 254 [pS], T2 = 123 [pS],
draft sel
f
SUE
CPU
(78)
2-84
[/4s]
T3= 2