Epson LQ-2550 Technical Manual page 250

CPU Timing
Two oscillator cycles define one state.
One machine cycle, such as OP (operational) code fetch or memory read/write, requires three states.
a) OP code fetch timing
lines AO to Al 8. During the latter half of state T1, the ME and ~ signals go active, and the memory
is accessed.
The OP codes on the data busses are fetched at the trailing clock of state T2.
The ~ signal goes active from the first half of state T1 to that of state T3, and indicates that this cycle
is an OP code fetch cycle.
b) Memory Data Read/Write Timing
The memory data access timing is different from the OP code fetch timing in the following points:
. The LIR signal does not go active.
. Read data is valid a half clock later, as comparing with the OP code fetch timing. (The data is fetched
at the trailing clock of state T3.)
For memory data write timing, the ME signal and WR signal are activated at the latter half of state T1
and the first half of state T2, respectively, and the write data is output on DO to 07 from the latter half
of state T 1. The ME and WR signals go inactive in the latter half of state T3, and the write data remains
valid on the data bus unitl just before state T 1 starts.
4
DO- D7
WAIT
RD
OP code fetch cycle
x
Ao - A18
0 0 - D?
- - - - - - - -
- - - - - - - -
m
\
Figure A-3. OP Code Fetch Timing
Read circle
I
— - - - - - -
- - — - - -
,
1
I
I
Figure A-4. Memory Data Read/Write Timing
I
1
x
I I
I I
I
I
1 - - - - - - - - - - - - - - - -
I
I
/
1 1
I
W r i t e c i r c l e
I_
12 13
,
x
1
- - i----L--
i
I
A-5
x
- - - - - - - -
- - - - — - - -
/