Advanced Chipset Features - ECS 649-M2 Manual

Advanced Chipset Features

These items define critical timing parameters of the motherboard. You should leave the
items on this page at their default values unless you are very familiar with the technical
specifications of your system hardware. If you change the values incorrectly, you may
introduce fatal errors or recurring instability into your system.
DRAM Clock/Drive Control [Press Enter]
System BIOS Cacheable
Video RAM Cacheable
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
F5:Previous Values
DRAM Clock/Drive Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
DDR CAS Latency
DRAM Timing Control
x RAS to CAS Delay (tRCD)
x Precharge Time (tRP)
x RAS Active Time (tRAS)
Write Recovery Time (tWR)
x
Command Bypass
Data Bypass
UMC0 MA Timing
UMC0 Read Data Ready
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
F5:Previous Values
DDR CAS Latency (SPD)
This item controls the timing delay (in clock cycles) before the DRAM starts a read
command after receiving it.
DRAM Timing Control (Auto)
Enables you to select the CAS latency time in HCLKs of 2, 2.5, or 3. The value is set at
the factory depending on the DRAM installed. Do not change the values in this field
unless you change specifications of the installed DRAM or the installed CPU.
• RAS to CAS Delay (tRCD) (2T): This is the amount of time a CAS is per-
formed after a RAS. The lower the better, but some DRAM does not support
low figures.
Phoenix-AwardBIOS CMOS Setup Utility
Advanced Chipset Features
[Disabled]
[Disabled]
F6:Fail-Safe Defaults
Phoenix-AwardBIOS CMOS Setup Utility
DRAM Clock/Timing Control
[By SPD]
[Auto]
2T
2T
15T
1T
[Disabled]
[Disabled]
[Auto]
[Auto]
F6:Fail-Safe Defaults
Using BIOS
Item Help
Menu Level
F7:Optimized Defaults
Item Help
Menu Level
F7:Optimized Defaults
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