Advanced Chipset Features Option - ECS P6VXM2 Manual

Advanced Chipset Features Option

This option displays a table of items that define critical timing pa-
rameters of the mainboard components including the memory,
and the system logic. Generally, you should leave the items on
this page at their default values unless you are very familiar with
the technical specifications of your system hardware. If you
change the values incorrectly, you may introduce fatal errors or
recurring instability into your system.
CMOS Setup Utility – Copyright (C) 1984 – 2000 Award Software
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
SDRAM Cycle Length
DRAM Clock
Memory Hole
P2C/C2P Concurrency
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP-4X Mode
AGP Driving Control
x AGP Driving Value
AGP Fast Write
OnChip USB
USB Keyboard Support
OnChip Sound
OnChip Modem
↑ ↓ → ← : Move Enter : Select
F5:Previous Values
Bank 0/1 2/3 DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers. The ti m-
ings programmed into this register are dependent on the system design.
Slower rates may be required in certain system designs to support
loose layouts or slower memory.
SDRAM Cycle Length
This item sets the timing and wait states for SDRAM memory. We rec-
ommend that you leave this item at the default value.
DRAM Clock
This item sets the DRAM Clock. We recommend that you leave this
item at the default value.
Advanced Chipset Features
SDRAM 8/10ns
SDRAM 8/10ns
3
Host CLK
Disabled
Enabled
Enabled
Enab led
64M
Enabled
Auto
DA
Disabled
Enabled
Disabled
Auto
Auto
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults
47
Item Help
Menu Level
F1:General Help
F7:Optimized Defaults
Default: 8/10 ns
Default: 3
Default: Host CLK