ECS 649-M2 Manual page 42

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Command Bypass(Disabled)
When enabled, request will bypass the command queue if the queue is empty.
Data Bypass (Disabled)
When enabled, the latency of read data from DRAM back to CPU will be lower.
UMC0 MA Timing (Auto)
This option allows you to set the lead off DRAM read and write cycles. When set to Delay
1T, memory read/write commands are sent one clock cycle behind the memory address.
When set to Normal, read/write and memory address commands are sent simultaneously.
UMC0 Read Data Ready (Auto)
This item defines the channel A DRAM read data latency.
Press <Esc> to return to the Advanced Chipset Features page.
System BIOS Cacheable (Disabled)
This item allows the system to be cached in memory for faster execution. Enable this item
for better performance.
Video RAM Cacheable (Disabled)
These items allow the video BIOS and RAM to be cached in memory for faster execution.
Enable these items for better performance.
Precharge Time (tRP) (2T): This is the duration of the time interval during
which the Row Address Strobe signal to a DRAM is held low during normal
Read and Write Cycles. This is the minimum interval between completing one
read or write and starting another from the same (non-page mode) DRAM.
Techniques such as memory interleaving, or use of Page Mode DRAM are
often used to avoid this delay. Some chipsets require this parameter in order
to set up the memory configuration properly. The RAS Precharge value is
typically about the same as the RAM Access (data read/write) time.
RAS Active Time (tRAS) (15T) : This item allows you to set the amount of
time a RAS can be kept open for multiple accesses. High figures will improve
performance.
Write Recovery Time (tWR)(1T): This item defines DRAM internal write to
read command delay in the same device.
Using BIOS