Table 14. System Memory Map; Table 15. I/O Map; Dma Channels; Pci Configuration Space Map - Intel S875WP1LX Specification

S875WP1-E TPS
4. Maps and Interrupts
In this section, Table 14 describes the system memory map, Table 15 shows the I/O map, Table
16 lists the DMA channels, Table 17 defines the PCI configuration space map, and Table 18
describes the interrupts.
4.1 Memory Map
Address Range Address Range
(decimal)
1024 K - 4194304 K 100000 - FFFFFFFF
960 K - 1024 K F0000 - FFFFF
896 K - 960 K E0000 - EFFFF
800 K - 896 K C8000 - DFFFF
640 K - 800 K A0000 - C7FFF
639 K - 640 K 9FC00 - 9FFFF
512 K - 639 K 80000 - 9FBFF
0 K - 512 K 00000 - 7FFFF
4.2 I/O Map
Address (hex)
0000 - 00FF 256 bytes
0170 - 0177 8 bytes
01F0 - 01F7 8 bytes
(Note 1)
0228 - 022F 8 bytes
(Note 1)
0278 - 027F 8 bytes
(Note 1)
02E8 - 02EF 8 bytes
02F8 - 02FF (Note 1) 8 bytes
0376 1 byte
0377, bits 6:0 7 bits
0378 - 037F 8 bytes
03B0 - 03BB 12 bytes
03C0 - 03DF 32 bytes
03E8 - 03EF 8 bytes
03F0 - 03F5 6 bytes
Revision 4.0

Table 14. System Memory Map

Size
(hex)
4095 MB Extended memory
64 KB Runtime BIOS
64 KB Reserved
96 KB Available high DOS memory (open to the PCI bus)
160 KB Video memory and BIOS
1 KB Extended BIOS data (movable by memory manager
software)
127 KB Extended conventional memory
512 KB Conventional memory

Table 15. I/O Map

Size
Used by the Server Board S875WP1-E. Refer to the ICH5-R data
sheet for dynamic addressing information.
Secondary IDE channel
Primary IDE channel
LPT3
LPT2
COM4/video (8514A)
COM2
Secondary IDE channel command port
Secondary IDE channel status port
LPT1
Intel 82875P MCH
Intel 82875P MCH
COM3
Diskette channel 1
Maps and Interrupts
Description
Description
35