Intel S5000XVNSATA Specification page 94

Intel® Workstation Board S5000XVN TPS
Sensor Sensor System
Name Number Applicability
Memory C EEh System-
Error specific
Memory D EFh System-
Error specific
B0 DIMM F0h All
Sparing
Enabled
B0 DIMM F1h All
Sparing
Redun-
dancy
B1 DIMM F2h All
Sparing
Enabled
B1 DIMM F3h All
Sparing
Redun-
dancy
B01 DIMM F4h All
Mirroring
Enabled
B01 DIMM F5h All
Mirroring
Redun-
dancy
Revision 1.5
Sensor Type Event/Reading Event Offset
Type
Memory Sensor Correctable ECC
Specific
0Ch Uncorrectable
6Fh ECC
Memory Sensor Correctable ECC
Specific
0Ch Uncorrectable
6Fh ECC
Entity Sensor Entity present
Presence Specific
25h 6Fh
Memory Discrete 0Bh Fully redundant
0Ch
Non-red: suff res
from redund
Non-red: suff res
from insuff res
Non-red: Insuff
res
Entity Sensor Entity present
Presence Specific
25h 6Fh
Memory Discrete 0Bh Fully redundant
0Ch
Non-red: suff res
from redund
Non-red: suff res
from insuff res
Non-red: insuff
res
Entity Sensor Entity present
Presence Specific
25h 6Fh
Memory Discrete 0Bh Fully redundant
0Ch
Non-red:suff res
from redund
Non-red:suff res
from insuff res
Intel order number: D66403-006
Criticality Assert/
Triggers De-assert
OK As
OK As
OK As
OK As
Degraded
Crtical
OK As
OK As
Degraded
Crtical
OK As
OK As
Degraded
Appendix B: BMC Sensor Tables
Readable Event Data Rearm
Value/Offsets
– Trig Offset A
– Trig Offset A
– Trig Offset A
– Trig Offset A
– Trig Offset A
– Trig Offset A
– Trig Offset A
– Trig Offset A
Standby
–
–
–
–
–
–
–
–
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