Functional Architecture; Figure 10. Functional Block Diagram - Intel S5000XVNSATA Specification

Workstation board

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Intel® Workstation Board S5000XVN TPS

Functional Architecture

The architecture and design of the Intel

Workstation Board S5000XVN is based on the Intel

S5000X chipset. This chipset is designed for systems that use the Intel

Xeon

processor with

system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz.

The chipset contains two main components: the Memory Controller Hub (MCH) for the host

bridge and the I/O controller hub for the I/O subsystem. The chipset uses the Enterprise South

Bridge (ESB2-E) for the I/O controller hub. This chapter provides a high-level description of the

functionality associated with each chipset component and the architectural blocks that make up

the server board.

For more information about the functional architecture blocks, see the Intel

S5000 Server

Board Family Datasheet.

Revision 1.5

Intel order number: D66403-006

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S5000xvnsatar S5000xvn