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Functional Architecture
In the following table, the following codes are used:
VP: Validated configuration and the slot is populated
SP: Supported, but not validated configuration, and the slot is populated
NP: Slot is not populated
Branch 0
Channel A
DIMM_A1
DIMM_A2
DIMM_B1
VP
NP
NP
VP
NP
VP
SP
SP
SP
VP
NP
VP
SP
SP
SP
VP
VP
VP
Notes:
Single channel mode is only tested and supported with a 512 MB x8 FBDIMM installed in DIMM Socket A1.
The supported memory configurations must meet population rules defined above.
For best performance, you should install a minimum of four DIMMs across memory branches.
Although mixed DIMM capacities between channels are supported, Intel
20
Table 7. DIMM Population Rules
Channel B
Channel C
DIMM B2
DIMM C1
NP
NP
NP
NP
NP
NP
SP
NP
NP
NP
VP
NP
SP
SP
NP
VP
VP
VP
Intel order number: D66403-006
Branch 1
Channel D
DIMM C2
DIMM D1
DIMM D2
NP
NP
NP
NP
NP
NP
VP
NP
SP
NP
VP
VP
®
does not validate FBDIMMs in mixed DIMM configurations.
Intel® Workstation Board S5000XVN TPS
Mirroring Possible
Sparing Possible
No
No
No
No
No
SP, Yes, Branch 0 only
VP, Yes
No
No
SP, Yes, Branch 0 only
VP, Yes
VP, Yes, Branch 0 and
Branch 1
Revision 1.5
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