Figure 14. Recommended Four Dimm Configuration - Intel S5000XVNSATA Specification

Fuctional Architecture
Branch 0
Functionally, DIMM sockets A2 and B2 could have been populated instead of DIMM sockets C1
and D1. However, the system would not achieve equivalent performance. Figure 13, on the
previous page, shows the supported DIMM configuration that is recommended because it allows
both branches to operate independently and simultaneously. FBD bandwidth is doubled when
both branches operate in parallel.
3.1.3.4.1 Mirrored Mode Memory Configuration
When operating in mirrored mode, both branches operate in lock step. In mirrored mode, branch
1 contains a replicate copy of the data in branch 0. The minimum DIMM configuration to support
memory mirroring is four DIMMs, populated as shown in Figure 14. All four DIMMs must be
identical with respect to size, speed, and organization.
To upgrade a four DIMM mirrored memory configuration, you must add four additional DIMMs to
the system. All four DIMMs in the second set must be identical to the first with the exception of
speed. The MCH adjusts to the lowest speed DIMM.
3.1.3.4.2 Sparing Mode Memory Configuration
The MCH provides memory sparing capabilities. Sparing is a RAS feature that involves
configuring a DIMM to be placed in reserve so it can be used to replace a DIMM that fails.
DIMM sparing occurs within a given bank of memory and is not supported across branches.
There are two supported memory sparing configurations.
Single Branch Mode Sparing
Dual Branch Mode Sparing
22
Branch 1

Figure 14. Recommended Four DIMM Configuration

Intel order number: D66403-006
Intel® Workstation Board S5000XVN TPS
Channel B
Channel A
Channel C
Channel D
TP02301
Revision 1.5