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3.9
CMOS Signals
CMOS input signals are shown in
AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for at least three BCLKs in order for
the processor to recognize them. See
groups.
3.10
Maximum Ratings
Table 6
lists the processor's maximum environmental stress ratings. The processor
should not receive a clock while subjected to these conditions. Extended exposure to
the maximum ratings may affect device reliability. Furthermore, although the processor
contains protective circuitry to resist damage from Electro-Static Discharge (ESD), one
should always take precautions to avoid high static voltages of electric fields.
Table 6.
Processor DC Absolute Maximum Ratings
Symbol
T
STORAGE
V
CC
V
inAGTL+
V
inAsynch_CMOS
Notes:
1.
For functional operation, all processor electrical, signal quality, mechanical and thermal specifications
must be satisfied.
2.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the
processor.
3.
Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not
affect the long term reliability of the device. For functional operation, please refer to the processor
case temperature specifications.
3.11
Processor DC Specifications
Note:
The processor DC specifications in this section are defined at the processor core (pads)
unless noted otherwise.
See
Table 5
on the FSB are in the AGTL+ signal group. The DC specifications for these signals are
listed in
Table
Table 7
through
1.66 GHz/1.83 GHz and are valid only while meeting specifications for junction
temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM)
and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating
frequencies supported on a particular processor. Active mode load line specifications
apply in all states. V
power up in order to set the VID values. Unless specified otherwise, all specifications
for the Intel
should be taken to read all notes associated with each parameter.
The Intel
SpeedStep
®
®
Intel
Celeron
Processor 1.66 GHz/1.83 GHz
DS
20
®
Intel
Celeron
Parameter
Processor storage
temperature
Any processor supply
voltage with respect to V
AGTL+ buffer DC input
voltage with respect to V
CMOS buffer DC input
voltage with respect to V
for the pin signal definitions and signal pin assignments. Most of the signals
8. DC specifications for the CMOS group are listed in
Table 10
list the DC specifications for the Intel
is the default voltage driven by the voltage regulator at
CC,BOOT
®
®
Celeron
Processor 1.66 GHz/1.83 GHz are at Tjunction = 100 °C. Care
®
®
Celeron
Processor 1.66 GHz/1.83 GHz does not support Enhanced Intel
®
Technology (EIST), therefore HFM and LFM transitions are not supported.
®
Processor 1.66 GHz/1.83 GHz—Electrical Specifications
Table
5. Legacy output FERR#, IERR# and other non-
Section 3.11
for the DC for the CMOS signal
Min
-40
-0.3
SS
-0.1
SS
-0.1
SS
Max
Unit
Notes
85
°C
2
1.6
V
1
1.6
V
1, 2
1.6
V
1, 2
Table
9.
®
®
Celeron
Processor
January 2007
Order Number: 315876-002
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